Clock feedthrough analysis and cancellation in current sample/hold circuits

Implementations of artificial neural networks using current-mode pulse width modulation technique

“…To maintain adequate accuracy, can be set to 1 pF to keep the charge injection at a minimum [7], or a simple clock feedthrough cancellation technique can be used to further improve the accuracy [20]. For improvement, one can use a more accurate current S/H such as the one in [21] which is shown her in Fig. 8.…”

“…A current S/H circuit for both signal-dependent and independent clock feed through current cancellation[21]. Charge injection in the CM-PWM circuit.…”

Improved StrongARM latch comparator: Design, analysis and performance evaluation

“…The clock feedthrough effect is due to the gate-source (or gate-drain) coupling, through the internal capacitance. There are many wellknown techniques to reduce the clock feedthrough problem such as connecting capacitors/transistors at the gate of the charging transistors [7,8], or replacing the charging transistors with transmission gates [9]. However, by adding any transistor (or capacitor), the total capacitance in the circuit is increased, and hence, the speed of the latch is decreased.…”

High speed switched-current memory cell with very low offset and charge injection errors

“…1(a) and (b), respectively. Although advantages of the 1st-generation SI memory cell include a low level of transient glitches [5], a possible nonunity current gain [6] and a simple single-phase clock scheme, a disadvantage is the need for two memory transistors (i.e. M 1 and M 2 ) that are unavoidable to mismatch errors and more power consumptions.…”