The use of a current-mode pulse width modulation (CM-PWM) technique to implement analog artificial neural networks (ANNs) is presented. This technique can be used to efficiently implement the weighted summation operation (WSO) that are required in the realization of a general ANN. The sigmoidal transformation is inherently performed by the nonlinear transconductance amplifier, which is a key component in the current integrator used in the realization of WSO. The CM-PWM implementation results in a minimum silicon area, and therefore is suitable for very large scale neural systems. Other pronounced features of the CM-PWM implementation are its easy programmability, electronically adjustable gains of neurons, and modular structures. In this paper, all the current-mode CMOS circuits (building blocks) required for the realization of CM-PWM ANNs are presented and simulated. Four modules for modular design of ANNs are introduced. Also, it is shown that the CM-PWM technique is an efficient method for implementing discrete-time cellular neural networks (DT-CNNs). Two application examples are given: a winner-take-all circuit and a connected component detector.
It is advantageous to use oversampling techniques with either AX or broadband data converters in both wireline and wireless digital receivers. This paper discusses the oversampling techniques for all-digital implementation of symbol timing recovery in digital receivers. The idea of oversampling techniques for timing recovery is to adjust the timing phases while decimating the oversampled signals. The spurious signal introduced by adjusting the CIC's (cascaded integrator-comb) timing phase has been analyzed and was found to be a serious problem. In this paper, a dual-differentiator timing phase adjustable decimation filter has been proposed and was used for symbol timing recovery. Simulations were provided to verify the validity of the proposed method.
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