A new single Miller capacitor for frequency compensation of three-stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three-stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain-bandwidth product (GBW) with just a very small amount of compensation capacitor. A three-stage amplifier has been simulated with and without a differential feedback path in a 0.18 μm complementary metal-oxide-semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83°PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON-CHIP compensation in comparison to other methods.
A new frequency compensation scheme using a second generation differential current conveyor (DCCII) for three-stage amplifiers is proposed. By adding a DCCII as a feedback path from output of the second and the third stage to the output of the first stage, feed-forward path and the right-half plane zero will be removed subsequently which improves phase margin and the gain-bandwidth product. Calculations are derived for two states. First state, a DCCII and two miller capacitors form the feedback paths and in the second state, two nulling resistors are series with miller capacitors. Analyses show that in both states, stability can be perfectly ensured.To demonstrate advantages of this technique over the traditional RNMC architecture, a three-stage amplifier is designed and simulated employing the proposed technique in a standard 0.18μm CMOS process. Simulation results show that, with the same load capacitance, the new amplifier has improved stabilities over the conventional RNMC amplifiers by more than 22° and 0.23MHz in the phase margin and gain-bandwidth product, respectively. The proposed amplifier dissipates less than 0.45 mW of power with a 1.8 V supply.
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