CHOP: Adaptive filter-based DRAM caching for CMP server platforms

Jiang, Xiaowei; Madan, Niti; Zhao, Li; Upton, Mike; Iyer, Ravishankar; Makineni, Srihari; Newell, Don; Solihin, Yan; Balasubramonian, Rajeev

doi:10.1109/hpca.2010.5416642

Cited by 112 publications

(123 citation statements)

References 27 publications

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“…Prior approaches toward reducing metadata storage overhead have managed the DRAM cache using large cache lines on the order of kilobytes [1,4] or represented the presence of smaller sectors of a large cache block as a bit vector, eliminating the need to store full tag metadata [7,13]. These techniques still store metadata for all of DRAM, increasing bandwidth consumption and pollution of the DRAM cache, increasing false-sharing probability, and limiting scalability.…”

Section: Related Workmentioning

confidence: 99%

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Meza

Chang

Yoon

et al. 2012

IEEE Comput. Arch. Lett.

146

112

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Abstract-Hybrid main memories composed of DRAM as a cache to scalable non-volatile memories such as phase-change memory (PCM) can provide much larger storage capacity than traditional main memories. A key challenge for enabling high-performance and scalable hybrid memories, though, is efficiently managing the metadata (e.g., tags) for data cached in DRAM at a fine granularity. Based on the observation that storing metadata off-chip in the same row as their data exploits DRAM row buffer locality, this paper reduces the overhead of fine-granularity DRAM caches by only caching the metadata for recently accessed rows on-chip using a small buffer. Leveraging the flexibility and efficiency of such a fine-granularity DRAM cache, we also develop an adaptive policy to choose the best granularity when migrating data into DRAM. On a hybrid memory with a 512MB DRAM cache, our proposal using an 8KB on-chip buffer can achieve within 6% of the performance of, and 18% better energy efficiency than, a conventional 8MB SRAM metadata store, even when the energy overhead due to large SRAM metadata storage is not considered.

show abstract

Section: Related Workmentioning

confidence: 99%

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Meza

Chang

Yoon

et al. 2012

IEEE Comput. Arch. Lett.

146

112

View full text Add to dashboard Cite

show abstract

“…As a result, they are primarily optimized for low cache-memory bandwidth utilization through block-based organizations, 7,8 sector-based footprintpredicting organizations, 4,6 and addresscorrelated filter-based caching mechanisms. 11 Unfortunately, such organizations come with high tag and/or metadata overhead and high design complexity, making such cache designs impractical. For instance, state-of-the-art block-based and footprintpredicting caches require 4 Gbytes and 200 Mbytes of tags, respectively, for a capacity of 32 Gbytes.…”

Section: State-of-the-art Dram Cachesmentioning

confidence: 99%

Fat Caches for Scale-Out Servers

et al. 2017

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“…This capacity constraint precludes the use of die-stacked DRAM as main memory. Hence, most proposals advocate employing die-stacked DRAM as a cache to filter out accesses to offchip main memory [10], [11], [20], [24].…”

Section: Background and Motivationmentioning

confidence: 99%

“…As a result, researchers have been exploring various ways to use the die-stacked DRAM as a giant last-level cache [10], [11], [19], [20], [24], [33]. There are a number of fundamental challenges that these past works have tried to address:…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

Jevdjic¹,

Loh

Kaynak³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

138

106

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Abstract-Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, diestacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of off-chip bandwidth. Today's stacked DRAM cache designs fall into two categories based on the granularity at which they manage data: block-based and page-based. The state-of-the-art block-based design, called Alloy Cache, colocates a tag with each data block (e.g., 64B) in the stacked DRAM to provide fast access to data in a single DRAM access. However, such a design suffers from low hit rates due to poor temporal locality in the DRAM cache. In contrast, the state-of-the-art page-based design, called Footprint Cache, organizes the DRAM cache at page granularity (e.g., 4KB), but fetches only the blocks that will likely be touched within a page. In doing so, the Footprint Cache achieves high hit rates with moderate on-chip tag storage and reasonable lookup latency. However, multi-gigabyte stacked DRAM caches will soon be practical and needed by server applications, thereby mandating tens of MBs of tag storage even for page-based DRAM caches.We introduce a novel stacked-DRAM cache design, Unison Cache. Similar to Alloy Cache's approach, Unison Cache incorporates the tag metadata directly into the stacked DRAM to enable scalability to arbitrary stacked-DRAM capacities. Then, leveraging the insights from the Footprint Cache design, Unison Cache employs large, page-sized cache allocation units to achieve high hit rates and reduction in tag overheads, while predicting and fetching only the useful blocks within each page to minimize the off-chip traffic. Our evaluation using server workloads and caches of up to 8GB reveals that Unison cache improves performance by 14% compared to Alloy Cache due to its high hit rate, while outperforming the state-of-the art page-based designs that require impractical SRAM-based tags of around 50MB.

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CHOP: Adaptive filter-based DRAM caching for CMP server platforms

Cited by 112 publications

References 27 publications

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

Fat Caches for Scale-Out Servers

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

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