Fat Caches for Scale-Out Servers

Volos, Stavros; Jevdjic, Djordje; Falsafi, Babak; Grot, Boris

doi:10.1109/mm.2017.32

Cited by 17 publications

(18 citation statements)

References 10 publications

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“…Without loss of generality, we consider a DRAM cache with its tags stored in SRAM, a common design choice in prior work [15,30,34,36,72]. For the DRAM cache's memory controller, we use a critical-block-first policy and FR-FCFS open-row scheduling with page-based interleaving.…”

Section: Evaluation Methodologymentioning

confidence: 99%

“…Prior work on DRAM-only systems showed the performance superiority of two-tier memory hierarchies, comprised of a 3D stacked DRAM cache such as Hynix' HBM [3] or Micron's HMC [49], and a second tier of planar DRAM delivering the necessary memory capacity [34,58,72]. In our experiments, a two-tier hierarchy with 3D stacked DRAM as a first tier cache, and conventional planar DRAM as a second tier outperforms single-tier planar DRAM by 30%, corroborating prior work [34,72].…”

Section: Designing Scms To Meet Key Requirementsmentioning

confidence: 99%

“…Capacity is a first-order determinant of the cache's filtering efficiency, while block size introduces a tradeoff between leveraging spatial locality and data overfetch. Prior work on 3D$s investigated the impact of these parameters for DRAM-based systems [33,34,46,58,72]. We revisit these key design parameters for 3D$s in the different context of SCM-based systems, where main memory capacity and access latencies are significantly higher.…”

Section: D Stacked Dram Cache Designmentioning

confidence: 99%

“…Using terminology commonly used in the literature, we argue that DRAM caches should be architected as page caches [36,43,72] rather than block caches, where the term page refers to the cache block size being significantly larger than a typical cache block size of 64B. Page-based caches are superior due to the much lower miss ratios exhibited when the cache block size exceeds 1KB.…”

Section: D Stacked Dram Cache Designmentioning

confidence: 99%

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Design guidelines for high-performance SCM hierarchies

Ustiugov¹,

Daglis²,

Picorel

et al. 2018

Proceedings of the International Symposium on Memory Systems

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With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a few factors of DRAM. Nevertheless, the latency-sensitive nature of memory-resident services makes seamless integration of SCM in servers questionable. In this paper, we ask the question of how best to introduce SCM for such servers to improve overall performance/cost over existing DRAM-only architectures. We first show that even with the most optimistic latency projections for SCM, the higher memory access latency results in prohibitive performance degradation. However, we find that deployment of a modestly sized high-bandwidth 3D stacked DRAM cache makes the performance of an SCM-mostly memory system competitive. The high degree of spatial locality that memory-resident services exhibit not only simplifies the DRAM cache's design as page-based, but also enables the amortization of increased SCM access latencies and the mitigation of SCM's read/write latency disparity.We identify the set of memory hierarchy design parameters that plays a key role in the performance and cost of a memory system combining an SCM technology and a 3D stacked DRAM cache. We then introduce a methodology to drive provisioning for each of these design parameters under a target performance/cost goal. Finally, we use our methodology to derive concrete results for specific SCM technologies. With PCM as a case study, we show that a two bits/cell technology hits the performance/cost sweet spot, reducing the memory subsystem cost by 40% while keeping performance within 3% of the best performing DRAM-only system, whereas single-level and triple-level cell organizations are impractical for use as memory replacements.• Information systems → Storage class memory; Cloud based storage; • Hardware → Memory and dense storage; KEYWORDS Storage-class memory, heterogeneous memory hierarchy, 3D stacked DRAM ACM Reference Format:

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Section: Evaluation Methodologymentioning

confidence: 99%

Section: Designing Scms To Meet Key Requirementsmentioning

confidence: 99%

Section: D Stacked Dram Cache Designmentioning

confidence: 99%

Section: D Stacked Dram Cache Designmentioning

confidence: 99%

See 2 more Smart Citations

Design guidelines for high-performance SCM hierarchies

Ustiugov¹,

Daglis²,

Picorel

et al. 2018

Proceedings of the International Symposium on Memory Systems

Self Cite

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“…This is because the popularity distribution of objects is highly skewed, typically following power law distributions [5,21,37,43]. In other words, in the presence of skew, the server(s) serving the most popular objects will become saturated, thus becoming a bottleneck and limiting the throughput of the entire KVS.…”

Section: Introductionmentioning

confidence: 99%

Scale-out ccNUMA

Gavrielatos

Katsarakis

Joshi

et al. 2018

Proceedings of the Thirteenth EuroSys Conference

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Today's cloud based online services are underpinned by distributed key-value stores (KVS). Such KVS typically use a scale-out architecture, whereby the dataset is partitioned across a pool of servers, each holding a chunk of the dataset in memory and being responsible for serving queries against the chunk. One important performance bottleneck that a KVS design must address is the load imbalance caused by skewed popularity distributions. Despite recent work on skew mitigation, existing approaches offer only limited benefit for high-throughput in-memory KVS deployments.In this paper, we embrace popularity skew as a performance opportunity. Our insight is that aggressively caching popular items at all nodes of the KVS enables both load balance and high throughput -a combination that has eluded previous approaches. We introduce symmetric caching, wherein every server node is provisioned with a small cache that maintains the most popular objects in the dataset. To ensure consistency across the caches, we use high-throughput fully-distributed consistency protocols. A key result of this work is that strong consistency guarantees (per-key linearizability) need not compromise on performance. In a 9-node RDMA-based rack and with modest write ratios, our prototype design, dubbed ccKVS, achieves 2.2× the throughput of the state-ofthe-art KVS while guaranteeing strong consistency.

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