Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

Abstract

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS). The use of a high-k dielectric material, specially Al2O3, in the blocking oxide concentrates the electric fields across the tunnel oxide and SiN, and releases it across the blocking oxide under program and erase mode. This effect leads to lower program and erase voltage as well as faster erase speed than the conventional SiO2∕SiN∕SiO2 (SONOS) device. Moreover, it is shown that the fast erase operation is performed even at a thicker tunnel oxide over 30Å where the hole direct tunneling current through the tunnel oxide is reduced significantly and thus the SANOS device has the excellent bake retention.

Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission

“…At an electric field of 1 MV/cm; tunneling over a potential barrier of 1.36 eV is negligible. 3,22,23 In fact, when a very small negative gate voltage is applied in order to program it, the holes (charged particles) in the channel gain enough energy and drift towards channel/tunnel oxide interface, but their energy is not enough for tunneling through the 3.6-nm-thick tunnel oxide to the charge trapping layer due to the large barrier (DE v ¼ 1.36 eV). However, at lower electric fields, thermal emission of holes over the barrier is dominant.…”

A SONOS device with a separated charge trapping layer for improvement of charge injection

“…8 Use of a high-k dielectric layer as the blocking oxide of SONOS increases the E-field across the tunneling oxide, leading to fast erase speed. 9 In a bandgap engineered (BE)-SONOS device, the tunneling oxide of SONOS is replaced by a BE ONO layer. 10 Efficient hole tunneling occurs under the high E-field due to the band offset of the BE ONO layer, which allows fast erase speed.…”

The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

“…For example, HfO 2 , ZrO 2 , Y 2 O 3 and La 2 O 3 have been employed to replace Si 3 N 4 in SONOS memory devices to acquire better trapping characteristics, [21][22][23] and Al 2 O 3 has been employed as the tunneling layer and the blocking layer to reduce the working voltage. 24 For a charge-trapping memory (CTM) device, the charge-trapping layer with a high charge-trapping capability in a small scale is critically important for further applications in the future.…”