The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

Abstract

The charge-trapping memory devices namely Pt/Al 2 O 3 /(Al 2 O 3 ) 0.5 (Cu 2 O) 0.5 /SiO 2 /pSi with 2, 3 and 4 nm SiO 2 tunneling layers were fabricated by using RF magnetron sputtering and atomic layer deposition techniques. At an applied voltage of ±11 V, the memory windows in the C-V curves of the memory devices with 2, 3 and 4 nm SiO 2 tunneling layers were about 4.18, 9.91 and 11.33 V, respectively. The anomaly in memory properties among the three memory devices was ascribed to the different back tunneling probabilities of trapped electrons in the charge-trapping dielectric (Al 2 O 3 ) 0.5 (Cu 2 O) 0.5 due to the different thicknesses of SiO 2 tunneling layer.

Research on c-HfO2 (0 0 1)/α-Al2O3 (1 -1 0 2) interface in CTM devices based on first principle theory

“…Recently, except for the mono-layered HfO 2 trapping layer, [7][8][9] experimental studies has been extended to high-k composites [10][11][12][13][14] or multi-layered high-k materials. 1,[15][16][17][18][19] Thus, the interface HfO 2 /Al 2 O 3 , which plays an important role in charge trapping behavior, is likely to appear in different parts of CTM stacked structures.…”