Charge instability of atomic-layer deposited TaSiOx insulators on Si, InP, and In0.53Ga0.47As

Abstract

Low barriers for electrons are found to be the reason for significant charge instability at interfaces of (100)InP and (100)In0.53Ga0.47As with atomic-layer deposited TaSiOx insulators. The formation of these reduced barriers is associated with the growth of a narrow-bandgap interlayer between the semiconductor and TaSiOx, which enables electron tunneling at low electric fields and subsequent trapping in the insulator. A wide-gap passivation layer may be required to improve the performance of TaSiOx as gate insulator.

In Situ SiO2 Passivation of Epitaxial (100) and (110)InGaAs by Exploiting TaSiOx Atomic Layer Deposition Process

“…This approach has been successfully demonstrated using atomic layer deposited amorphous TaSiO x on (i) InP/InGaAs/InAlAs quantum well FETs, 3 (ii) InGaAs FinFETs, 4,5 and (iii) GaAsSb/InGaAs tunnel FETs. 9,10 Moreover, successful integration of high-κ dielectrics, for example., Al 2 O 3 , 11−13 HfO 2 14 and TaSiO x 3−5,15−18 on crystallographically oriented (100)In x Ga 1– x As and (110)In x Ga 1– x As would aid in paving the way for In x Ga 1– x As FinFET adoption, of which a representative device architecture is shown in Figure 1.…”

“…The rationale for using low band gap In x Ga 1– x As (0.53 ≤ x ≤ 1.0) is its superior electron mobility (μ n ), allowing for higher transistor drive current ( I ON ) at lower operating voltages during n-channel field-effect transistors (FETs) operation. − Furthermore, the μ n of In x Ga 1– x As epilayers has been demonstrated to be dependent on the epilayer’s crystallographic orientation. , Additionally, high-κ gate dielectric/semiconductor heterointerface engineering approaches have been adopted to passivate surface dangling bonds at the dielectric/semiconductor heterointerface by forming an in situ or ex situ interface passivating layer (IPL) to achieve high interfacial quality and superior gate electrostatics with interface defect densities, D it , as low as ∼4 × 10 11 cm –2 eV –1 . This approach has been successfully demonstrated using atomic layer deposited amorphous TaSiO x on (i) InP/InGaAs/InAlAs quantum well FETs, (ii) InGaAs FinFETs, , and (iii) GaAsSb/InGaAs tunnel FETs. , Moreover, successful integration of high-κ dielectrics, for example., Al 2 O 3 , − HfO 2 and TaSiO x − ,− on crystallographically oriented (100)­In x Ga 1– x As and (110)­In x Ga 1– x As would aid in paving the way for In x Ga 1– x As FinFET adoption, of which a representative device architecture is shown in Figure .…”

“…Although atomic layer deposited TaSiO x high-κ dielectric layers have been investigated on the (100)­In x Ga 1– x As/InP system, − the majority of the reported work has utilized chlorine (Cl)-based precursors, namely TaCl 5 and SiCl 4 − wherein the reaction byproducts formed during the process can have a detrimental impact on the dielectric quality, including but not limited to thickness nonuniformity and nonideal oxide stoichiometry (i.e., oxide charge) . To circumvent these issues, we propose the adoption of Cl-free precursors, such as tantalum­(V) ethoxide (Ta 2 (OC 2 H 5 ) 10 ) and tris­( tert -butoxy)­silanol (Si­(OH)­(OC­(CH 3 ) 3 ) 3 ), for the atomic layer deposition (ALD) of TaSiO x .…”

Atomic layer deposition of tantalum oxide and tantalum silicate from TaCl5, SiCl4, and O3: growth behaviour and film characteristics

“…[1][2][3][4][5] Recently, Ta 2 O 5 -based materials have generated renewed interest for applications in transistor and memory. [6][7][8][9][10][11][12] TaSiO x has recently been studied as the gate dielectric in advanced metal-oxide-semiconductor eld effect transistors (MOSFETs) due to its interface characteristics with high-mobility III-V channels like InP, GaAs, and InGaAs. [6][7][8] Furthermore, Ta 2 O 5based oxides have shown promise for high density resistive random-access memory (RRAM) application with respect to endurance, retention, and switching speed.…”

“…[6][7][8][9][10][11][12] TaSiO x has recently been studied as the gate dielectric in advanced metal-oxide-semiconductor eld effect transistors (MOSFETs) due to its interface characteristics with high-mobility III-V channels like InP, GaAs, and InGaAs. [6][7][8] Furthermore, Ta 2 O 5based oxides have shown promise for high density resistive random-access memory (RRAM) application with respect to endurance, retention, and switching speed. [10][11][12] In the last decade, atomic layer deposition (ALD) has become the reference deposition technique to fabricate dielectric lms for nanoelectronic applications because it allows for excellent thickness and uniformity control, good physical/chemical and electrical properties of the layers at low deposition temperatures, and conformal growth on complex three-dimensional structures.…”