Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure

Abstract

Ultrathin channel trench junctionless poly-Si fieldeffect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness (T CH ) and gate length (L G ). These devices (L G = 0.5 µm) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high I ON /I OFF current ratio (10 6 A/A) and practically negligible drain-induced barrier lowering (∼0 mV/V). The I ON current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications. Index Terms-Trench junctionless field-effect transistor (trench JL-FET), nanowires (NWs), and three-dimensional (3-D).

Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application

“…Figure 8 presents the output I D -V D characteristics of the trench and conventional Fe-FinFET devices both with L G = 400 nm at V OV (V GS −V T ) from 0.1 to 0.5 V with a step of 0.1 V for comparison. The trench Fe-FinFET had a saturation current approximately 2.3 greater than the conventional Fe-FinFET at V OV = 0.5 V. This higher I ON can be attributed to the higher electron velocity and electron density in the trench, especially around the valleys of the trench [16]. TCAD simulations (Synopsys, Mountain View, CA, USA) were performed to further understand how the trench structure improves the electrical characteristics.…”

“…To further improve its performance, an Fe-FinFET with a trench structure (trench Fe-FinFET) is proposed in this work. Most FETs with a trench structure produced to date [15][16][17][18] have been designed as junctionless, ultra-thin channel transistors to ensure that the channel is fully depleted and to suppress short channel effects (SCEs). However, this design may result in degraded carrier mobility [19] and lower on current (I ON ).…”

Comprehensive Study of Stacked Nanosheet-Type Channel Based on Junctionless Gate-All-Around Thin-Film Transistors

“…The NS channel structure is preferable in terms of 1) effective channel width, 2) process simplicity, and 3) design flexibility [1]- [3]. Additionally, the junctionless thin-film transistor (JL-TFT) has the advantages of low thermal budget, long effective channel length, and a simple source and drain engineering [9]- [11]. Accordingly, this study compared the electrical characteristics of the single-NS and stacked-NS JL structures and subsequently investigated the electrical behavior of the stacked-NS JL channel with multi-gate and gate-all-around (GAA) TFTs.…”

Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact

“…Because of the special doping profile, JL-FETs have several advantages such as a low thermal budget that can integrate with high-k/metal-gate more easily than can conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), a longer effective channel length than conventional MOSFETs, and the avoidance of complicated S/D engineering. To solve the JL-FET turn-off problem, an ultrathin body structure is required to achieve a fully-depleted channel region in the off state [ 15 , 16 , 17 ]. However, the drive current (I D ) declines as transistor features are scaled.…”