Characterizing 3D Floating Gate NAND Flash

Xiong, Qin; Wu, Fei; Lu, Zhonghai; Zhu, Ying; Zhou, You; Chu, Yibing; Xie, Conghua; Huang, Ping

doi:10.1145/3162616

Cited by 37 publications

(7 citation statements)

References 23 publications

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“…Ma [40] tested and analyzed the RBER(raw bit error rate) of 3D TLC NAND Flash and also proposed a life prediction scheme of 3D TLC NAND Flash based on RBER and SVM(support vector machine), the experiment results showed that the prediction scheme can significantly extend the lifetime of flash blocks. Q. Xiong et al [37] studied the delay and raw bit error rate of 3D NAND based on floating gate and they obtained similar results with 2D NAND. Toru [41] studied and analyzed the problems that should be paid attention to when developing the next generation of 3D NAND Flash from the perspective of power consumption, performance and reliability.…”

Section: Related Workmentioning

confidence: 77%

“…Venkatesan [36] discussed the fundamentals and electron properties of 3D NAND Flash from the view of fabrication process integration and equipment engineering. References [11,37,38] compared 2D NAND Flash and 3D NAND Flash in terms of physical structure and working principle, and analyzed the advantages and problems brought by 3D technology. Seo [39] studied the interference between flash cells in terms of the composition of 3D NAND Flash cells.…”

Section: Related Workmentioning

confidence: 99%

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Measurement and Analysis of SSD Reliability Data Based on Accelerated Endurance Test

et al. 2019

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In recent years, NAND Flash-based solid-state drives (SSDs) have become more widely used in data centers and consumer markets. Data centers generally choose to provide high-quality storage services by deploying a large number of SSDs, but there are no effective preventive measures to reduce the impact of SSD failures currently. Some existing studies have analyzed the relevant factors related to SSD failures from different angles, but the characteristics of reliability changes exhibited by SSD throughout the life cycle have not been explored in depth. On the other hand, although the 3D manufacturing process has increased the storage density of the SSD, the mutual influence between the flash units has also increased, resulting in severe degradation of the performance and lifetime of the SSD. Therefore, in order to fully understand the reliability varying process of SSD throughout the life cycle, we first designed an SSD lifetime endurance test method, then conducted the endurance test and collected the reliability data for the entire life cycle of the 3D TLC SSD in the laboratory environment with reference to the JEDEC standard. Through the analysis of experimental data and its statistical correlation, it is found that SSD will produce a large number of uncorrectable errors before reaching the endurance limit, and there will be a phenomenon of continuous high operating temperature, as well as showing some intrinsic relationships about SSD reliability data. The findings in this paper are valuable for identifying whether an SSD is going to fail.

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Section: Related Workmentioning

confidence: 77%

Section: Related Workmentioning

confidence: 99%

Measurement and Analysis of SSD Reliability Data Based on Accelerated Endurance Test

et al. 2019

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“…Chen et al [12] optimized the garbage collection performance in the view of block erase efficiency and proposed a multi-block erase strategy. Xiong et al [29] and Wu et al [30] studied the characteristics and challenges of 3D flash memories with the floating-gate (FG) type and the charge-trap (CT) type, respectively. Hung et al [31] studied the cross-layer process variation problems of 3D vertical-gate flash and proposed three layer-aware program-andread scheme to reduce P/E cycle numbers and to improve read performance.…”

Section: Related Workmentioning

confidence: 99%

Observation and Optimization on Garbage Collection of Flash Memories: The View in Performance Cliff

Liu

Gao

et al. 2021

Micromachines

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The recent development of 3D flash memories has promoted the widespread application of SSDs in modern storage systems by providing large storage capacity and low cost. Garbage collection (GC) as a time-consuming but necessary operation in flash memories largely affects the performance. In this paper, we perform a comprehensive experimental study on how garbage collection impacts the performance of flash-based SSDs, in the view of performance cliff that closely relates to Quality of Service (QoS). According to the study results using real-world workloads, we first observe that GC occasionally causes response time spikes, which we call the performance cliff problem. Then, we find that 3D SSDs exacerbate the situation by inducing a much higher number of page migrations during GC. To relieve the performance cliff problem, we propose PreGC to assist normal GC. The key idea is to distribute the page migrations into the period before normal GC, thus leading to a reduction in page migrations during the GC period. Comprehensive experiments with real-world workloads have been performed on the SSDsim simulator. Experimental results show that PreGC can efficiently relieve the performance cliff by reducing the tail latency from the 90th to 99.99th percentiles while inducing a little extra write amplification.

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“…Two recent works compare the retention loss phenomenon between 3D NAND and planar NAND flash memory [65,70] through real device characterization, and report findings similar to our work regarding the early retention loss phenomenon. Two other recent works use a methodology similar to ours to characterize 3D NAND devices based on different 3D NAND flash memory cell technologies (i.e., 3D floating-gate cell and 3D vertical gate cell) [38,94,95], which are less common than the 3D charge trap NAND flash memory cell technology that we test in this paper. Other recent works [23,31,78,80,92] report several differences of 3D NAND flash memory from planar NAND flash memory.…”

Section: Related Workmentioning

confidence: 99%

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

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Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory.In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell.Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

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Characterizing 3D Floating Gate NAND Flash

Cited by 37 publications

References 23 publications

Measurement and Analysis of SSD Reliability Data Based on Accelerated Endurance Test

Measurement and Analysis of SSD Reliability Data Based on Accelerated Endurance Test

Observation and Optimization on Garbage Collection of Flash Memories: The View in Performance Cliff

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

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