Characterization of the annealing behavior for copper-filled TSVs

Abstract

Herein we describe the annealing behavior of copper Through Silicon Vias (TSVs) in a series of experiments. Temperatures ranged from 150°C to 450°C and the dwell of the temperature varied between 30 min and 4 h. Copper protrusion, test samples warpage and the copper microstructure were examined in a subsequent characterization. Combining the results of these measurements enables the determination of an optimized temperature and dwell set, which avoids further protrusion and minimizes stress after annealing. Additionally, the data analysis shows a temperature- and dwell-dependency of copper protrusion and die warpage. Electron backscatter diffraction (EBSD) measurements on TSV cross sections show changes of the micro structure. Hence it could be verified that copper underwent grain growth during annealing. The described investigations represent a new systematic approach for the characterization of the copper annealing behavior in TSVs. The evaluation of the specific expe riments and the comparison between different annealing conditions enable insights into the structural changes of the material during the annealing process. With help of the implemented characterization this approach succeeds in giving optimized settings for the TSV annealing process. Based on the measurement data it is possible to choose a suitable temperature and dwell process set depending on subsequent redirection layer (RDL) processing steps. Furthermore a model for the annealing procedure in TSVs is derived from the measurement results

μ-Raman spectroscopy and FE-modeling for TSV-Stress-characterization

“…But current investigations allow the conclusion that besides microstructure changes in copper also a stress minimum is present at annealing temperature [1,2,10]. So the stress-free state of the model was set to 250°C and cooling down to room temperature served as thermal load profile.…”

“…But the annealing procedure subsequent to Cu fill and overburden CMP is still necessary to stabilize Cu's material behavior. Due to material CTE-mismatches (Cu-SiO 2 -Si) and the annealing behavior of Cu, mechanical stresses are induced during annealing [1,2]. In order to avoid defects like layer delaminations or even Si cracking it is important to quantify these loads.…”

Backside TSV protrusion induced by thermal shock and thermal cycling

“…Barrier layer between Cu pad and Cu TSV grain boundaries below the Cu recrystallization temperature (T R ), and grain growth sets in above T R [16,23], leaving voids at grain boundaries. Fig.…”

“…In addition, it is desirable to correlate the experimental data in terms of thermal test conditions and determine new failure mechanisms. In particular, previous TSV reliability studies have reported problems with TSV protrusions on the TSV frontside, which have been resolved by optimizing the electroplating chemistry and annealing conditions [16][17][18]. However, there has been no report on protrusions at the TSV backside.…”

Bath chemistry and copper overburden as influencing factors of the TSV annealing

“…To prevent this effect to occur an additional annealing is conducted, which stabilizes the crystal structure of Cu. But this approach has also drawbacks since mechanical stresses are induced due to the CTE mismatches of the materials (Cu-SiO2-Si) [4,5]. This results in an increased risk for the occurrence of delaminations as well as increased wafer warpage.…”