Characterization of Half-Select Free Write Assist 9T SRAM Cell

Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Transistors Sizingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

“…The read access time is measured as the time required for RBL to fall by 50 mV when RWL turns ON 16 . Read access failure occurs if RBL fails to discharge below 50 mV or discharges below this value even before RWL is turned ON 8 .…”

Section: Performance Evaluationmentioning

confidence: 99%

A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

Gupta

Pandey

2021

Summary The conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Self Cite

In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is