Characterization of bit transistors in a functional SRAM

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are reviewed in this paper. Transistor and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by padded-out cells and minimum operating voltages for the entire array. Correlations between various components of variability are essential for adding appropriate margins to the design.

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Technology variability from a design perspective

Nikolić

Giraud

Guo

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

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Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM

Zimmer

Thomas

Toh

et al. 2014

2014 44th European Solid State Device Research Conference (ESSDERC)

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On-chip in-situ measurements of V<inf>th</inf> and AC gain of differential pair transistors

Bandô

Takaya

Ohkawa

et al. 2010

2010 International Conference on Microelectronic Test Structures (ICMTS)

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In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, V th , of 1.0-V transistors in a 90-nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus V th of transistors within amplifiers is captured. The degradation of common-mode rejection property is observed for an amplifier with intentionally introduced mismatches to the pair of transistors.

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Characterization of bit transistors in a functional SRAM

Cited by 10 publications

References 2 publications

Technology variability from a design perspective

Technology variability from a design perspective

Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM

On-chip in-situ measurements of V<inf>th</inf> and AC gain of differential pair transistors

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