Characterization of a Silicon Carbide BCD Process for 300°C Circuits

Abbasi, Affan; Mantooth, Alan; Roy, Sajib; Murphree, Robert; Rashid, Arman Ur; Hossain, Maksudal; Lai, Pengyu; Fraley, John; Erlbacher, Tobias; Chen, Zhong

doi:10.1109/wipda46397.2019.8998920

Cited by 13 publications

(10 citation statements)

References 15 publications

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“…The blocking voltage of the lot2 HV NMOS exceeds 600 V, offering significantly higher output power comparing to the typical Si power ICs. The maximum drain current and blocking voltage of the HV NMOS in this work are significantly higher than the SiC lateral power MOSFETs reported in the recently developed SiC Bipolar-CMOS-DMOS (BCD) process [23].…”

Section: B High-voltage Mosfetsmentioning

confidence: 58%

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Liu

Zhang

Isukapati

et al. 2022

IEEE J. Electron Devices Soc.

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Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600 V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.

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Section: B High-voltage Mosfetsmentioning

confidence: 58%

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Liu

Zhang

Isukapati

et al. 2022

IEEE J. Electron Devices Soc.

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“…The photodetectors are implemented in the novel open silicon carbide CMOS technology [9][10][11] developed by Fraunhofer IISB in Germany. The fabrication process front-end-of-line (FEOL) is implemented by ion implantation, which is used for the photodetector realization.…”

Section: Device Fabricationmentioning

confidence: 99%

“…Unfortunately, the HiTSiC technology was discontinued in 2018, which left the need for a new and open SiC CMOS technology. This need is addressed by the recent development of the SiC CMOS at Fraunhofer IISB [9][10][11]. This work reports on a quadrant sun position sensor in 4H-SiC (Figure 1), which builds on the previously reported integrated 3D optics approach [12] to aim for miniaturization of the device in the future.…”

Section: Introductionmentioning

confidence: 99%

Visible Blind Quadrant Sun Position Sensor in a Silicon Carbide Technology

Romijn

Vollebregt

May

et al. 2022

2022 IEEE 35th International Conference on Micro Electro Mechanical Systems Conference (MEMS)

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In this paper, we present a quadrant sun position sensor microsystem device in a silicon carbide technology that operates in a field-of-view of ±33° and reaches a mean error of 1.9° in this range. This will allow, for the first time, an inherently visible blind sun position sensor in a CMOS compatible technology. Opto-electronic integration of the photodetectors and CMOS readout circuitry on-chip is vital to compete with the performance of silicon state-of-the-art and for the concept to be adopted by industry, which is where previous implementations of visible blind sun sensors are lacking.

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“…The power transistors and LV peripheral devices are integrated into a single chip. Figure 25 shows the HVIC BCD process platform based on SiC material [96,97] . BCD devices are formed by the same compatible process.…”

Section: Hv Integration Beyond Siliconmentioning

confidence: 99%

Review of technologies for high-voltage integrated circuits

Zhang

Zhu

et al. 2022

Tsinghua Sci. Technol.

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High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

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Characterization of a Silicon Carbide BCD Process for 300°C Circuits

Cited by 13 publications

References 15 publications

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

Visible Blind Quadrant Sun Position Sensor in a Silicon Carbide Technology

Review of technologies for high-voltage integrated circuits

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