Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness

Lin, Horng−Chih; Lin, Chiung–Wei; Lin, Zer-Ming; Shie, Bo-Shiuan; Huang, Tiao-Yuan

doi:10.1109/ted.2013.2239647

Cited by 30 publications

(20 citation statements)

References 15 publications

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“…Thus, it can skip junction formation issues and greatly simplify fabrication. Recently, the JL poly-Si TFTs [1][2][3][4] have been shown as attractive devices because they possess excellent turn-on and output characteristics, an improved subthreshold swing, a large ON-current, a high ON/OFF-current ratio, etc. Also, it is feasible to apply JL scheme for large-area electronics as well as 3D stackable poly-Si based electronics.…”

Section: Introductionmentioning

confidence: 99%

“…Also, it is feasible to apply JL scheme for large-area electronics as well as 3D stackable poly-Si based electronics. 1 As a counterpart of JL poly-Si TFTs, JL MOSFETs have several compact models. [5][6][7] A compact model, unlike a simple device model or a comprehensive computer simulation model used for understanding the device physics, provides both accuracy and computational efficiency due to the limited simulation time.…”

Section: Introductionmentioning

confidence: 99%

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Surface potential calculation and drain current model for junctionless double-gate polysilicon TFTs

Deng

Huang

2014

AIP Advances

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Surface potential is a key parameter in evaluating the DC property of thin-film transistors (TFTs). In this paper, for the junctionless symmetric double-gate polysilicon TFTs, a physical-based explicit calculation to surface potential has been derived. Incorporating impurity concentration, mobile charge and trap density into Poisson's equation, a closed form of band bending as a function of gate voltage is obtained and demonstrated as an accurate and computationally efficient solution. Based on surface potential, a drain current model for long-channel devices is provided in explicit forms. Furthermore, it is verified successfully by comparisons with both 2D numerical simulation and experimental data in different operation regions.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Surface potential calculation and drain current model for junctionless double-gate polysilicon TFTs

Deng

Huang

2014

AIP Advances

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“…In addition, the electric potential at the boundary of the depletion region is also zero because the device layer has been electrically grounded through the drain and the source terminal (φ(X dep ) = 0). By using φ(x = 0) = φ s and E(x = X dep ) = 0, we can solve the system of equations shown in Equation (A12) [12]:…”

Section: Appendix a Depletion Region Width Analytical Formulamentioning

confidence: 99%

“…On the other hand, the implementation of two-dimensional (2D) or planar solutions have been recently investigated by numerous researchers because they are simple and easy to fabricate [9][10][11][12]. During the last decade, numerous implementations of junctionless transistors were proposed such as single gate [10,11], double gate [13], thin-film [12], tunnel-FET [14], just to mention a few. These structures are characterized by different geometries; however, their operation is based on the same working principle, which consists of varying the dimensions of the depletion region in order to control the flow of the current through the transistor.…”

Section: Introductionmentioning

confidence: 99%

“…In order to provide an analytical formula, which describes the operation of a JLT, some researchers have proposed introducing a few simplistic assumptions. Among the others, the complete depletion assumption is the most significant hypothesis that allows for extracting an approximated analytical formula for the depletion region width [12,[16][17][18][19]. Although this approximated model have been mentioned and utilized in numerous scientific articles, its accuracy was never formally analyzed, at least to the best knowledge of the authors.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

et al. 2019

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In this paper, we investigate the accuracy of the approximated analytical model currently utilized, by many researchers, to describe the depletion region width in planar junctionless transistors (PJLT). The proposed analysis was supported by numerical simulations performed in COMSOL Multiphysics software. By comparing the numerical results and the approximated analytical model of the depletion region width, we calculated that the model introduces a maximum RMS error equal to 90 % of the donor concentration in the substrate. The maximum error is achieved when the gate voltage approaches the threshold voltage ( V t h ) or when it approaches the flat band voltage ( V F B ) of the transistor. From these results, we concluded that this model cannot be used to determine accurately the flat-band and the threshold voltage of the transistor, although it represents a straightforward method to estimate the depletion region width in PJLT. By using the approximated analytical model, we extracted an analytical formula, which describes the electron concentration at the ideal boundary of the depletion region. This formula approximates the numerical data extracted from COMSOL with a relative error lower than 1 % . The proposed formula is in our opinion, as useful as the formula of the approximated analytical model because it allows for estimating the position of the depletion region also when the drain and source terminals are not grounded. We concluded that the analytical formula proposed at the end of this work could be useful to determine the position of the depletion region boundary in numerical simulations and in graphical representations provided by COMSOL Multiphysics software.

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Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective

Kumar

Gupta²,

Rai

2021

Silicon

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Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness

Cited by 30 publications

References 15 publications

Surface potential calculation and drain current model for junctionless double-gate polysilicon TFTs

Surface potential calculation and drain current model for junctionless double-gate polysilicon TFTs

Analysis of an Approximated Model for the Depletion Region Width of Planar Junctionless Transistors

Comparative Analysis & Study of Various Leakage Reduction Techniques for Short Channel Devices in Junctionless Transistors: A Review and Perspective

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