Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel

Lin, Horng−Chih; Lin, Chiung–Wei; Huang, Tiao‐Yuan

doi:10.1109/led.2011.2171914

Cited by 69 publications

(37 citation statements)

References 8 publications

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“…These devices feature a heavily doped channel with doping type and concentration identical to those of the source/drain to eliminate the S/D junctions, and are proposed to overcome the problems associated with the formation of p/n junctions in conventional inversion-mode devices. Although the preliminary efforts were mainly on nano-scale MOS devices, more recently we've also demonstrated the feasibility of this approach for poly-Si-based JL devices [4], [5]. Considering the excellent high current drive and the elimination of implant steps in fabrication, the polySi JL devices are a promising alternative for future 3D-IC and flat-panel products.…”

Section: Introductionmentioning

confidence: 98%

Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors

Lin

Huang

2013

ECS Trans.

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In this work, we study the electrical characteristics of planar poly-Si junctionless (JL) thin-film transistors (TFTs) with 10 nm-thick channel and various gate width. The output current of JL devices is drastically larger than that of the control device with an undoped channel, owing to the abundant carriers contained in the channel of the JL devices which tends to reduce both channel and source/drain series resistances. Subthreshold swing of the JL devices is found to be larger than the control ones, owing to the existence of a depletion layer in the channel. Nonetheless, excellent on/off current ratio (>1E+07) is achieved, thanks to the use of the ultra-thin channel.

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Section: Introductionmentioning

confidence: 98%

Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors

Lin

Huang

2013

ECS Trans.

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“…The JL structure has also been proposed in polycrystalline silicon (poly-Si) transistors, including planar and multiple gate devices [3]- [6]. In order to fully deplete the channel by gate electrostatic field, the channel dimension needs to be scaled down close to 10 nm [1].…”

Section: Introductionmentioning

confidence: 99%

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Liu

Pan

Sheu

2015

IEEE J. Electron Devices Soc.

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A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high I on /I off current ratio of 7 × 10 8 (V G = 4 V and V D = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.INDEX TERMS Gate-all-around (GAA), poly-Si, junctionless (JL), nanowire (NW), sidewall spacer, transistor.

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“…Such JL features are also demonstrated with polycrystalline silicon (poly-Si) thin-film transistors (TFTs) [4], [5], which are suitable for monolithic 3-D vertically stacked integrated circuits and to continue the applicability of Moore's law [6]. The adoption of NW geometries as the JL channel must be small enough to fully turn off the channel.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, large grains in the poly-Si channel are associated with superior performance, including a steep subthreshold swing (SS), a high ON-state current, owing to the accompanying reduction in defects [7]. Manuscript Hence, this letter investigates the poly-Si channel of JL TFTs utilizing dry oxidation to form the ultrathin channel instead of directly depositing the thin-film as the poly-Si channel in JL TFTs [4], [5] of small grain size suffered from the performance degradation mentioned above. The channel with nano-belt structure is also adopted to reduce the sensitivity of threshold voltage (V TH ) variations with fabrication parameters, i.e., if one of the channel dimensions is small enough, the variations of the other dimension do not impact too much V TH [8].…”

Section: Introductionmentioning

confidence: 99%

Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

Chen

Chang

et al. 2013

IEEE Electron Device Lett.

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This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10 8 because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the shortchannel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.Index Terms-Gate-all-around (GAA), junctionless (JL), thin-film transistor, ultrathin channel.

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Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel

Cited by 69 publications

References 8 publications

Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors

Characteristics of N-Type Planar Junctionless Poly-Si Thin-Film Transistors

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

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