Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Liu, Tung-Yu; Pan, Fu‐Ming; Sheu, Jeng−Tzong

doi:10.1109/jeds.2015.2441736

Cited by 26 publications

(8 citation statements)

References 16 publications

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“…The twin gate structure can also be applied to a double channel GAAFET, as shown in Figure 7b. A fabricated twin gate double channel GAAFET showed an I on /I o f f ratio of 7 × 10 8 , a DIBL of 83 mV/V, and a SS of 105 mV/dec [33]. Besides silicon and polysilicon channel junctionless GAAFETs, devices composed of other materials were also reported: a gallium arsenide junctionless GAAFET was simulated, leading a SS value near to the theoretical limit (58.2 mV/dec at 293.15 K) [27].…”

Section: Gate-all-aroundmentioning

confidence: 99%

“…This device turned out to be the first one of a new generation of transistors. In the last decades, many other junctionless devices were proposed, which includes FinFET , Gate-All-Around (GAA) [24][25][26][27][28][29][30][31][32][33][34][35][36][37], Single Gate (SGJLT) [38][39][40][41][42][43][44][45][46][47][48][49][50], Double Gate (DGJLT) , Thin Film (TFT) [76][77][78][79][80][81][82][83][84][85][86], and Tunnel FET (TFET) [87][88][89][90][91][92][93][94][95][96][97]. Because most of the review papers on JLTs were published in 2010-2014…”

Section: Introductionmentioning

confidence: 99%

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Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Gate-all-aroundmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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“…Recently, the JLMOSFETs have received significant attention for their technological feasibility and theoretical modeling. In the last decades, several device architectures for JLMOSFETs were proposed, such as Thin Film JLMOSFET [5], [6], FinFET [7], [8], Tunnel FET [9], [10], gate-all-around (GAA) FET [11], [12], singlegate JLT (SG-JLT) [13], [14], double-gate JLMOSFETs (DG-JLMOSFETs) [15]- [18], etc. The DG-JLMOSFETs are becoming more promising due to their superior performances in high speed and low power applications [19].…”

Section: Introductionmentioning

confidence: 99%

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Islam

Hasan²,

Islam

et al. 2021

IEEE Access

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In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for highperformance switching applications. The quantum transmitting boundary method (QTBM) has been considered for electron transport, and the band structures are accounted for sp3d5s * tight-binding modeling. The channel thickness, t ch is varied from 1.7 to 4.7 nm to evaluate the device figure of merits (FOMs). The thinner channel's device shows a lower OFF-state current, while the ticker channel device allows a higher ON-state current. The threshold voltage is approximately 0.4 V for GaAs DG-JLMOSFETs with t ch = 1.7 nm, whereas it reduces to ∼0.05 V for that of t ch = 4.7 nm. Similar characteristics have been shown in GaSb devices. Besides, a significant impact of t ch on the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is found in GaSb DG-JLMOSFETs compared with those of GaAs devices. The devices show a higher leakage-power dissipation in both channel materials and low-intrinsic delay for thicker t ch due to a substantial amount of energy drop. The above results indicate that III-V-based DG-JLMOSFETs are very promising for next-generation high-performance switching technology.INDEX TERMS GaAs, GaSb, double gate, junctionless MOSFETs, nano-scaled device, short-channel effects (SCEs), high-performance switching.

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“…Gola et al [14] investigated the effect of substrate bias voltage and induced surface potential on the threshold-voltage of Tri-gate junctionless FETs (TG-JLFETs). In specific, gate-all-around junctionless FETs (GAA-JLFETs) have been reported as promising structures for highperformance devices that considered their gate voltage controllability, exciting scalability, and improved carrier transport mechanism [15][16]. Trivedi et al [17] The analytical modeling results have been verified through the TCAD simulation results, where they found excellent agreement between mathematical and simulation results.…”

mentioning

confidence: 99%

A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs

Gupta

Awasthi

Kumar

et al. 2021

Silicon

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This present article interprets the analytical models of central channel potential, the threshold voltage, and subthreshold current for Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs. The parabolic approximation equation with appropriate boundary conditions has been adopted to solve the 2D Poisson's equation for determining the central channel potential. The minimum channel potential is obtained by potential channel expression, and it is utilized to determine the threshold voltage and subthreshold current by using the Drift-Diffusion method. The behaviour of GD-JL-GAA MOSFETs has been examined by varying physical device parameters such as doping concentration ( ), channel thickness ( ), oxide thickness ( ), and channel length ratio (L 1 : L 2 ). The mathematical analysis shows that the nominal gate leakage current in GD-JL-GAA MOSFETs due to high graded abrupt junction inside the channel region. The analytical model results have been verified with simulation data extracted from a TCAD simulator.

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Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Cited by 26 publications

References 16 publications

Junctionless Transistors: State-of-the-Art

Junctionless Transistors: State-of-the-Art

Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs

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