Challenges of Wafer Surface Preparation in Advanced Technologies

Abstract

Advanced technology nodes introduce new module processes, materials and integrated flow scheme to drive device performance, such as epitaxial SiGe, high-k metal gate (HKMG) or III-V substrate materials [1]. Conventional wet cleaning technologies can not fulfill requirements of new generational devices competently in such novel fields [2]. A case is SiGe epitaxial process prefers to grow on hydrogen-terminated surface of silicon wafer, and oxygen control in deionic water and cleaning aqueous solutions are most addressed and studied. In this presentation, the focuses are on wafer surface preparation for SiGe and HKMG applications and challenges of physcial force cleaning for nano devices.

A Design for Selective Wet Etching of Si3N4/SiO2in Phosphoric Acid Using a Single Wafer Processor

“…This issue also brings the precipitation of SiO 2 as a particle source on the wafer surface, that is more and more critical and important in the device yield with the shrinkage of pattern dimension. [15][16][17][18][19] Accordingly, it is necessary to keep the temperature stable in the process bath to avoid the formation of SiO 2 precipitates.…”