Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm

Nakahara, S.; Higeta, K.; Kohno, Makiko; Kawamura, T.; Kakitani, K.

doi:10.1109/test.1999.805644

Cited by 59 publications

(16 citation statements)

References 13 publications

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“…The architecture assumes that the cache is equipped with a BIST circuitry, which tests the entire cache and detects faulty cells based on the failure mechanisms described in Section II. Any conventional BIST [10], [11] can be employed to perform these tests. Since the number of faulty cells and their location changes depending on operating condition (e.g., supply voltage, frequency), such tests are conducted whenever there is a change in operating condition.…”

Section: Process-tolerant Cache Architecturementioning

confidence: 99%

“…A block is considered faulty even if only one bit in that block is faulty. The probability of a block to be faulty is given by (10) Hence, the probability of having a row that can be corrected (i.e., there is at least one nonfaulty block in a row having N blocks), is given by (11) and the probability that all M rows can be corrected is (12) There are blocks in the cache and hence, the size of the OBI is bits. Therefore, the probability that OBI is fault free is given by (13) and thus (14) (15) Table III shows the configuration of a 64-K cache with three different fault tolerant schemes.…”

Section: ) Eccmentioning

confidence: 99%

“…We propose a process-tolerant cache architecture suitable for high-performance memories, to detect and replace faulty cells by adaptively resizing the cache. This architecture assumes that the cache is equipped with an online built-in-self-test (BIST) [10], [11] to detect faulty cells due to process variation. The proposed scheme then downsizes the cache by forcing the column MUX to select a nonfaulty block in the same row if the accessed block is faulty.…”

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confidence: 99%

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A process-tolerant cache architecture for improved yield in nanoscale technologies

Agarwal

Paul

Mahmoodi

et al. 2005

IEEE Trans. VLSI Syst.

176

120

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Abstract-Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters.In this paper, we analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under inter = intra = 30 mV.

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Section: Process-tolerant Cache Architecturementioning

confidence: 99%

Section: ) Eccmentioning

confidence: 99%

mentioning

confidence: 99%

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A process-tolerant cache architecture for improved yield in nanoscale technologies

Agarwal

Paul

Mahmoodi

et al. 2005

IEEE Trans. VLSI Syst.

176

120

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“…In addition, most authors have solved the problem of detecting ADDFs by using a test called Moving Inversion 'MOVI' [4,7,8]. [9] even uses the time consuming GalPat test [5].…”

Section: Introductionmentioning

confidence: 99%

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

Goor¹,

Hamdioui

Gaydadjiev

et al. 2009

2009 Asian Test Symposium

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Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.

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“…However, faults in the address decoders and address decoder paths, denoted as Address decoder Faults 'AFs' have only gotten limited attention. Several authors have shown the importance of this class of faults [4,6,9,10,11,12]. Most authors have solved the problem of detecting Delay Faults in the Address decoders, denoted as 'AFDs', by using a test called Moving Inversion 'MOVI' [4,6,11].…”

Section: Introductionmentioning

confidence: 99%