A process-tolerant cache architecture for improved yield in nanoscale technologies

Agarwal, Amit; Paul, B.C.; Mahmoodi, Hamid; Datta, Animesh; Roy, Kaushik

doi:10.1109/tvlsi.2004.840407

Cited by 176 publications

(132 citation statements)

References 17 publications

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“…Agarwal et al propose a process-tolerant cache architecture using a cache line disabling technique, which statically detects and deletes cache lines with faulty cells [18]. In their scheme, the number of faulty cells and their locations are obtained and stored in a configurator by performing a conventional built-in self-test (BIST).…”

Section: Hard Error Management Techniquesmentioning

confidence: 99%

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Zhang

Ampadu

2014

JLPEA

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Abstract:We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead.

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Section: Hard Error Management Techniquesmentioning

confidence: 99%

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Zhang

Ampadu

2014

JLPEA

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“…Recently, Agarwal et al proposed a variation tolerant cache architecture [3]. Marculescu and Talpes discuss the merits of globallyasynchronous, locally synchronous (GALS) techniques to design processors under process variation [8].…”

Section: Related Workmentioning

confidence: 99%

Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation

Liang

Brooks

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Abstract-Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. This variability manifests itself by increasing the number and criticality of long delay paths. To quantify this impact, we use an architectural process variation model that is appropriate for the analysis of system performance in the earlystages of the design process. We propose a method of selecting microarchitectural parameters to mitigate the frequency impact due to process variability for distinct structures, while minimizing IPC (instructions-per-cycle) loss. We propose an optimization procedure to be used for system-level design decisions, and we find that joint architecture and statistical timing analysis can be more advantageous than pure circuit level optimization. Overall, the technique can improve the 90% yield frequency by about 14% with 3% IPC loss for a baseline machine with a 20FO4 logic depth per pipestage. This approach is sensitive to the selection of processor pipeline depth, and we demonstrate that machines with aggressive pipelines will experience greater challenges in coping with process variability.

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“…Their high access speed, high density and low energy consumption make them replacement candidates for SRAM, especially in view of advances made in 3-D stacking technology [6]. 1 One of the issues that continue to be a challenge for using these next-generation memory technologies is their yield. Due to the material and manufacturing process involved, there is greater amount of defects and process variations.…”

Section: Introductionmentioning

confidence: 99%

“…This higher density allows for the use of architectural means to recover yield losses. In this paper, we introduce the salvage cache, a micro-architectural technique for tolerating 1 Some of our references refer specifically to a variant of the MRAM called the spin torque transfer RAM (STT-RAM). We make no such distinction and shall refer to both as 'MRAM'.…”

Section: Introductionmentioning

confidence: 99%

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Koh¹,

Wong

Chen³

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-There has been much work on the next generation of memory technologies such as MRAM, RRAM and PRAM. Most of these are non-volatile in nature, and compared to SRAM, they are often denser, just as fast, and have much lower energy consumption. Using 3-D stacking technology, it has been proposed that they can be used instead of SRAM in large level 2 caches prevalent in today's microprocessors. However, one of the key challenges in the use of these technologies, such as MRAM, is their higher fault probabilities arising from the larger process variation, defects in its fabrication, and the fact that the cache is much larger. This seriously affect yield. In this paper, we propose a fault resilient set associative cache architecture which we called the salvage cache. In the salvage cache, a faulty cache block is sacrificed and used to repair faults found in other blocks. We will describe in detail the architecture of the salvage cache as well as provide results of yield simulations that show that a much higher yield can be achieved viz-a-viz other fault tolerant techniques. We will also show the performance savings that arise from the use of a large next-generation L2 cache.

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A process-tolerant cache architecture for improved yield in nanoscale technologies

Cited by 176 publications

References 17 publications

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

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