New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

Abstract

Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.

Optimizing memory BIST Address Generator implementations

“…E.g., for N =3 there are 6 CMs: 012, 021, 102, 120, 210, and 201. For memory testing, the AG has to generate several CMs, since each CM has its own fault detection capability [3], [6], [8], [9], [11], [20]. For this paper, the most common, and important, CMs will be considered; they are explained next.…”

“…In the world of MBIST, memory accesses have to be applied at-speed, using Back-to-Back (BtB) memory cycles [2]- [5], [7]- [9]. Systems require large, high speed memories, while current technology exhibits a large spread in implementation parameters, resulting in speed-related (i.e., delay) faults [3], [8], [11], [19]. Their detection is mandatory in today's industry [2], [4], [6], [20], and requires non-linear algorithms such as GalPat, GalRow and GalColumn, and a special Address Generator (AG).…”

On the Generation of SIC Pairs in Optimal Time

“…Sequences constituting of SIC pairs have been also applied to the testing of RAMs, to test either for address decoder faults [33], [34], or for pattern sensitive faults in memory cells [35], [36]. Due to the fact that only one bit changes between two consecutive vectors-therefore reducing the consumed energy-SIC sequences have been also utilized in low-power testing [37], [38], [39].…”

ALU based address generation for RAMs

“…In addition, memories are more susceptible to defects, and hence, to faults due to that they are designed with minimal design rule tolerances. In memory BIST, accesses are performed at-speed [2]- [5], [7]- [9], while the technology (45 nm and beyond) results in speed-related faults [3,8,11,19]. Therefore low-cost, memory BIST schemes should support a variety of algorithms, while allowing for a simple implementation.…”

“…Hence, the detection of different memory fault classes requires different address generators [3,6,8,9,11,20]. Table 1 highlights two of the most well-established counting methods by giving an example for a memory with N=4 words.…”