Optimizing memory BIST Address Generator implementations

Abstract

Memory Built-In Self-Test (MBIST) has become a standard industrial practice. Its quality is mainly determined by its fault detection capability in relationship to the the area overhead. The MBIST Address Generator (AG) is largely responsible for the fault detection capability, and has a significant contribution to the area overhead. This paper analyzes the properties and implementation aspects of several AGs. In addition, it presents a novel, very systematic, highspeed, low-power and low-overhead implementation, based on an Up-counter and a set of multiplexors.

Synthesis of Test Sequences with a Given Switching Activity

“…. a 2 a 1 a 0 generated in an arbitrary order, with each vector formed only once [2,6,19]. For example, the linear counting address sequence for m = 4 consists of 16 4-digit binary vectors 0000, 0001, 0010, 0011, .…”

“…. , 1111, each formed only once [6]. As a basis for the mathematical model we use a modified method of forming Sobol sequences [20][21][22].…”

“…An essential role for test sequences is played by switching activity, which affects the switching activity of the digital devices to be tested. The set of test sequences in the self-test architectures used includes sequences with different switching activity [5,6]. The set of such sequences includes: linear counting sequences, Gray code sequences, sequences with maximum switching activity (address complement sequences); sequences with Hamming distance equal to one for all pairs of addresses (2 i counting sequences), and a number of other sequences [3,5,6].…”

“…It should be noted that the study of the synthesis of various types of devices with variable values of switching activity for testing computer systems is only at the initial stage. In particular, the methods for synthesizing address sequence generators, discussed in a number of sources [6,[16][17][18], make it possible to construct such devices described by fixed values of switching activity. The problem of synthesizing devices for generating test sequences with a given switching activity and forming controlled probabilistic test sequences remains practically open.…”

Architecture for an efficient MBIST using modified March-y algorithms to achieve optimized communication delay and computational speed

“…In a circuit, testing of memory is more essential because the likelihood that the memory faults occur exceeds the likelihood of occurrence of other kinds of faults. But, MBIST can deliver the result to the above problem, as only little amount of I/O pins is present in a circuit (Van De Goor et al, 2011). In this paper, Section 2 would deal with the SRAM testing algorithms in recent research works and describes the various uses of industry standard testing algorithms designed for testing the configurable memory resources.…”