Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

Liu, Yangfan; Liu, Peng; Jiang, Yingtao; Yang, Mei; Wu, Kejun; Wang, Weidong; Yao, Qingdong

doi:10.1080/00207217.2010.512017

Cited by 23 publications

(8 citation statements)

References 13 publications

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“…Table 2 lists the software tool chains that we have used through the parallelization. Our experiments are conducted on the multi-FPGA-based networks-on-chip emulation platform [8]. Eight 32-bit compatible MIPS4Kc RISC cores were instantiated on the platform, which can be configured to 2, 4, and 8 cores.…”

Section: Resultsmentioning

confidence: 99%

Scalable-Grain Pipeline Parallelization Method for Multi-core Systems

Liu

Huang

Guo

et al. 2013

Lecture Notes in Computer Science

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How to parallelize the great amount of legacy sequential programs is the most difficult challenge faced by multi-core designers. The existing parallelization methods at the compile time due to the obscured data dependences in C are not suitable for exploring the parallelism of streaming applications. In this paper, a software pipeline for multilayer loop method is proposed for streaming applications to exploit the coarse-grained pipeline parallelism hidden in multi-layer loops. The proposed method consists of three major steps: 1) transform the task dependence graph of a streaming application to resolve intricate dependence, 2) schedule tasks to multiprocessor system-on-chip with the objective of minimizing the maximal execution time of all pipeline stages, and 3) adjust the granularity of pipeline stages to balance the workload among all stages. The efficiency of the method is validated by case studies of typical streaming applications on multi-core embedded system.

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Section: Resultsmentioning

confidence: 99%

Scalable-Grain Pipeline Parallelization Method for Multi-core Systems

Liu

Huang

Guo

et al. 2013

Lecture Notes in Computer Science

Self Cite

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“…In this scenario, there are proposals whose implementation are based on a single FPGA [11][12][13][14], following the aim of our work, or on multi-FPGA [15][16][17], used to develop larger systems. One example is seen in [12], where the authors design a 2x3 virtual channel based NoC prototype on an Altera Stratix II FPGA.…”

Section: Related Workmentioning

confidence: 99%

Network-on-chip emulation framework for multimedia SoC development

2013

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Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is designed and implemented on a low-cost FPGA device.The objective of this work is the design and implementation of a prototyping platform with NoC topology, which provides a demonstrator for the implementation of multimedia applications. The emulation platform will allow evaluation, comparison, and verification of different aspects of a NoC design for SoCs intended for the execution of multimedia applications.The proposed emulation platform consists of different type of functional IP blocks (microprocessors, memory blocks, peripherals, additional blocks, etc.) interconnected through an interconnection infrastructure based on NoC. In order to provide a low-cost solution, the platform design is restricted to use a single FPGA, resulting in a low-scale SoC due to the limited resources available in the FPGA used. However, the proposed design may be scalable and replicate in large scale FPGA or multi-FPGA devices to increase emulation performance.In this work, a design flow, which integrates different commercial EDA tools, is presented, and integration process is discussed in detail due to problems experienced in this stage. The platform is fully implemented on a Xilinx Spartan-6 LX45T FPGA and special attention is given to verification and floorplanning stages. Finally, various multimedia applications with real-time requirements are executed on the NoC-based SoC platform. At this stage, the performance results are analyzed according to the type of application, as well as the number of processors required.

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“…Hardware-based emulation using the evaluation platform is widely used to accelerate the validation process [9]. Emulation based on FPGA technology provides a rational way for the NoC.…”

Section: Related Workmentioning

confidence: 99%

“…With the development of FPGA technology, hardware-based emulation using the evaluation platform has become widely used. Compared with software simulation, it can accelerate the validation process as it significantly reduces the system evaluation time [9]. With shortening of the cycle of the NoC design, development costs will be reduced.…”

Section: Introductionmentioning

confidence: 99%

Task mapping and mesh topology exploration for an FPGA-based network on chip

Pang

Fresse

Yao

et al. 2015

Microprocessors and Microsystems

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International audienceTask mapping strategies on NoC (Network-on-Chip) have a huge impact on the timing performance and power consumption. So does the to-pology. In this paper, we describe the exploration flow of task mapping algorithms using different NoC mesh shapes. The flow is used to evaluate timing and energy consumption based on a NoC emulation platform. It is open to any task mapping algorithms and to any shapes of NoC mesh. A heterogeneous (PC and FPGA) platform is used to fully perform each step of the flow. The experiments demonstrate that the most appropriate task mapping strategy and the most suitable NoC shape strongly depend on the algorithm used. Depending on the timing latency results obtained and the FPGA resources used, the designer can select the appropriate task mapping strategy on the suitable shape in a short exploration time and with precise timing evaluation

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Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

Cited by 23 publications

References 13 publications

Scalable-Grain Pipeline Parallelization Method for Multi-core Systems

Scalable-Grain Pipeline Parallelization Method for Multi-core Systems

Network-on-chip emulation framework for multimedia SoC development

Task mapping and mesh topology exploration for an FPGA-based network on chip

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