Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer

Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

doi:10.1088/1361-6463/aa81ee

Cited by 7 publications

(5 citation statements)

References 22 publications

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“…The gas bubble gradually darkens from its edge and finally becomes part of the bonding region. This is very different from the situation in Si/Si wafer bonding with a-Ge bonding layer reported in our previous literature [39,40], in which the gas bubbles turn dark from the center and sprawl to the edge of the void. This is due to the fact that in Si/Si wafer bonding the a-Ge becomes polycrystalline Ge after bonding, while in Ge/Si wafer bonding, due to the introduction of the Ge substrate, the a-Ge turns into single-crystal Ge after bonding [36][37][38].…”

Section: Resultscontrasting

confidence: 89%

Double intermediate bonding layers for the fabrication of high-quality silicon-on-insulator-based exfoliated Ge film with excellent high-temperature characteristics

Zhou

Wang

et al. 2020

J. Phys. D: Appl. Phys.

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We investigate the high-temperature characteristics of wafer-bonded silicon-on-insulator (SOI)-based Ge film with two different intermediate bonding layers. For an amorphous Ge (a-Ge) bonding layer, due to the crystallization of a-Ge, many gas bubbles appear at the bonded interface to form Ge pits on the SOI. When the wafer pairs are annealed at ⩾400 °C, new gas bubbles appear and merge, leading to cracking of the Ge film due to the fact that the new gas bubbles cannot be transferred sufficiently rapidly out of the bonded interface of two single-crystal materials. For an a-Ge/a-Si bonding layer, the porous a-Si can serve as a reservoir at the bonded interface to absorb the by-products. With increase in a-Si layer thickness, the gas bubble density decreases. New gas bubbles are not observed after annealing at 500 °C when a 30 nm thick a-Si layer is introduced. More importantly, the quality of the Ge film with an a-Ge/a-Si bonding layer significantly improves after post-annealing. This can be explained by the repair of the point defects and restraining of the nucleation of threading dislocations by a-Si (no crystal orientation). This work presents high-quality heterogeneous hybrid integration of photoelectric materials by wafer bonding, which may give guidance for the low-temperature integration of Ge/Si, GeSn/Si and III–V/Si.

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Section: Resultscontrasting

confidence: 89%

Double intermediate bonding layers for the fabrication of high-quality silicon-on-insulator-based exfoliated Ge film with excellent high-temperature characteristics

Zhou

Wang

et al. 2020

J. Phys. D: Appl. Phys.

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“…In this method, a smooth semiconductor interlayer, which is formed by film deposition, ion implantation, or ion etching, was inserted between two Si wafers to achieve interlayer bonding. Tong et al [124] and our colleagues [125][126][127][128][129] systematically studied Si/Si wafer bonding based on an a-Si layer and on amorphous Ge (a-Ge), respectively. Tong et al studied the effect of a-Si interlayers fabricated by sputtering, ion implantation, RIE etching, and B 2 H 6 plasma treatment on the bonding strength and interface characteristics of Si/Si wafer pairs.…”

Section: Semiconductor Interlayer Bondingmentioning

confidence: 99%

A review: wafer bonding of Si-based semiconductors

Chen

2020

J. Phys. D: Appl. Phys.

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Wafer bonding techniques, which are very different from epitaxial growth techniques, can be used not only for the fabrication of micro-electromechanical systems (MEMS), silicon on insulator (SOI), and Si-based device integration, but have recently been applied to the achievement of high-quality homojunctions and heterojunctions in the photoelectric field. That is, carrier transport at the interface of the wafer-bonded junction should be unimpeded and carrier recombination at the bonded interface should be restrained. For Si/Si wafer bonding, although a high bonding strength and a bubble-free bonded interface are needed for the fabrication of the MEMS and SOI, a perfect Si/Si bonded interface which is expected to be bubble-free, oxide-layer-free, and dislocation-free is needed for the achievement of high-performance photoelectric devices, such as Ge/Si single-photon avalanche photodiodes. On the other hand, for Ge/Si heterogeneous hybrid integration (high lattice mismatch), threading dislocations (TDs) in the Ge film can be eliminated by low-temperature heterogeneous wafer bonding, due to the lower diffusion rate of misfit dislocations (MDs) at the Ge/Si bonded interface. This is very different from epitaxial growth, in which high-density TDs form in the integrated Ge layer due to the threading of MDs at high-temperature. In this paper, we review the wafer bonding of Si-based semiconductors based on different bonding methods. The advantages and disadvantages of different bonding methods are pointed out for comparison. We focus on the illustration of the fabrication of Si/Si and Ge/Si wafer pairs with TD-free, bubble-free, and oxide-layer-free bonded interfaces. Finally, the outlook for the development of Si/Si and Ge/Si wafer bonding and devices based on the wafer bonding technique is considered. We trust that this work may provide guidance for the low-temperature heterogeneous hybrid integration of different group materials with ultrahigh lattice mismatch, such as GeSn on Si and III-V materials on Si.

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“…In this paper, GaAs/Si bonded wafer was realized by introducing the amorphous Ge (a-Ge) intermediate layer [24,25]. There are two advantages of wafer bonding by introducing a-Ge.…”

Section: Introductionmentioning

confidence: 99%

Effect of the thermal stress on the defect evolution at GaAs/Si wafer bonding with a-Ge intermediate layer

Li¹,

Huang²,

Jiao³

et al. 2021

Semicond. Sci. Technol.

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In this paper, the bonding of GaAs wafer and Si wafer is achieved by introducing an amorphous Ge as the intermediate layer. Dislocations are observed on the GaAs surface when the GaAs/Si bonded wafers are annealed at 150 • C. The dislocation density is found to increase with the increase of the annealing temperature (from 150 • C to 350 • C). This feature can be explained by the increase of the thermal stress in the GaAs wafer due to the thermal mismatch between GaAs and Si wafers. With higher annealing temperature, such as 300 • C and 350 • C, some pits which originate from the partial cracking of GaAs surface are observed at the boundary of the bonded and unbonded regions. According to the stress simulation, the thermal stress at the bonding interface increases rapidly and reaches its maximum near the boundary of the bonded and unbonded regions, leading to the cracking of GaAs surface (formation of pits). In addition, large numbers of dislocations are generated near the pits. This may be attributed to the reduction of the nucleation energy of dislocations.

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Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer

Cited by 7 publications

References 22 publications

Double intermediate bonding layers for the fabrication of high-quality silicon-on-insulator-based exfoliated Ge film with excellent high-temperature characteristics

Double intermediate bonding layers for the fabrication of high-quality silicon-on-insulator-based exfoliated Ge film with excellent high-temperature characteristics

A review: wafer bonding of Si-based semiconductors

Effect of the thermal stress on the defect evolution at GaAs/Si wafer bonding with a-Ge intermediate layer

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