Breakthrough Integration of 32nm-node CulCntra Low-k SiOC (k=2.0) Interconnects by using Advanced Pore-Sealing and Low-k Hard Mask Technologies

Arakawa, Seiichi; Mizuno, Itaru; Ohoka, Y.; Nagahata, Kazunori; Tabuchi, K.; Kanamura, R.; Kadomura, S.

doi:10.1109/iitc.2006.1648690

Cited by 9 publications

(5 citation statements)

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“…This observation was utilized in hybrid integration approaches, which utilize a twolayer ILD comprised of an organosilicate layer at the via level and an organic polymer layer at the trench level [8,[123][124][125]. Although this approach limits plasma damage mainly to the via level (top and sidewall surfaces), it complicates the integration approach.…”

Section: Multilayer Structuresmentioning

confidence: 99%

Low‐kMaterials: Recent Advances

Dubois¹,

Volksen²

2012

Advanced Interconnects for ULSI Technology

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Section: Multilayer Structuresmentioning

confidence: 99%

Low‐kMaterials: Recent Advances

Dubois¹,

Volksen²

2012

Advanced Interconnects for ULSI Technology

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“…NH 3 plasma pore sealing has been found to prevent moisture uptake in ULK materials [ 110 ] and even to be resistant to limited DHF exposure [ 111 ]. The disadvantage of plasma pore sealing is that it tends to raise the effective dielectric constant, although low impact processes have been reported [ 112 ]. A potential advantage is mitigation of metal barrier coverage issues over porous surfaces [ 113 ].…”

Section: Plasma-induced Damage and Repairmentioning

confidence: 99%

Porous Dielectrics in Microelectronic Wiring Applications

McGahay

2010

Materials

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Porous insulators are utilized in the wiring structure of microelectronic devices as a means of reducing, through low dielectric permittivity, power consumption and signal delay in integrated circuits. They are typically based on low density modifications of amorphous SiO2 known as SiCOH or carbon-doped oxides, in which free volume is created through the removal of labile organic phases. Porous dielectrics pose a number of technological challenges related to chemical and mechanical stability, particularly in regard to semiconductor processing methods. This review discusses porous dielectric film preparation techniques, key issues encountered, and mitigation strategies.

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“…An additional challenge is ensuring adequate metal coverage on the sidewalls of porous low-k materials. Pore sealing prior to metallization is required to ensure good metal coverage (26). Because the barrier layers are deposited by physical vapor deposition , good control of the via and trench profiles is also critical in order to achieve adequate metal coverage (27).…”

Section: The Effect Of Processing On Stress-induced Voidsmentioning

confidence: 99%

Reliability of Copper Interconnects: Stress-Induced Voids

Gambino

Lee²,

Chen³

et al. 2009

ECS Trans.

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Stress-induced voids can form in Cu interconnects, due to either thermal expansion mismatch between the metal and the dielectric or due to confined grain growth in the Cu. The fail rate due to stress-induced voids increases as device dimensions decrease, because the critical void size to cause a fail decreases. Good process control is required for trench and via profiles, barrier and seed layer coverage, Cu fill, and cap layer adhesion, to prevent fails from stress-induced voids.

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Breakthrough Integration of 32nm-node CulCntra Low-k SiOC (k=2.0) Interconnects by using Advanced Pore-Sealing and Low-k Hard Mask Technologies

Cited by 9 publications

References 0 publications

Low‐kMaterials: Recent Advances

Low‐kMaterials: Recent Advances

Porous Dielectrics in Microelectronic Wiring Applications

Reliability of Copper Interconnects: Stress-Induced Voids

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