Bounding the shared resource load for the performance analysis of multiprocessor systems

Schliecker,; Negrean,; Ernst, F.

doi:10.1109/date.2010.5456951

Cited by 51 publications

(64 citation statements)

References 18 publications

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“…In this context, some previous work considers the entire memory system as a single resource, such that a processor core requests this resource when it generates a cache miss and it must hold this resource exclusively until the data of the cache miss are delivered to the processor core that requested it [32,5,9,37,23]. They commonly assumed that each memory request takes a constant service time and memory requests from multiple cores are serviced in the order of their arrival time.…”

Section: Related Workmentioning

confidence: 99%

“…Previous studies on bounding memory interference delay [9,43,32,37,5] model main memory as a blackbox system, where each memory request takes a constant service time and memory requests from different cores are serviced in either Round-Robin (RR) or First-Come FirstServe (FCFS) order. This memory model, however, is not safe for commercial-off-the-shelf (COTS) multi-core systems because it hides critical details necessary to place an upper This material is based upon work funded and supported by the Department of Defense under Contract No.…”

Section: Introductionmentioning

confidence: 99%

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Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

177

158

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Abstract-In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. We explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, we analyze the worstcase memory interference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

177

158

View full text Add to dashboard Cite

show abstract

“…To provide timing guarantees, several researchers, such as Pellizzoni et al [9], [10] and Schliecker et al [13], [14], have recently proposed methodologies to analyze the worstcase delay a task suffers due to accesses to a shared bus and shared memory, assuming synchronous resource accesses. Specifically, in [9], [10], a framework is developed to analyze the maximum delay that a task may suffer due to peripheral interference.…”

Section: Introductionmentioning

confidence: 99%

Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters

Schranzhofer

Pellizzoni

Chen

et al. 2011

2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium

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Abstract-Modern multiprocessor and multicore architectures adopt shared resources to meet increased performance requirements. Adaptive arbiters, such as FlexRay, have been adopted to grant access to shared resources. While increasing the performance, timing analysis is more challenging with this kind of arbiter. This paper considers real-time tasks that are composed of superblocks, while superblocks themselves are composed of phases. Phases are characterized by their worstcase computation time on their processing element and their worst-case number of access requests to a shared resource. Resource accesses, such as access to caches or scratchpad memory, are synchronous and cause the processing element to stall until the access is served. Based on dynamic programming, we develop an algorithm that safely derives an upper-bound of the worst-case response time of a phase. The worst-case response time of a task can then be determined for both sequential or time-triggered execution of superblocks. Experimental results are conducted for a real-world application.

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“…This approach enables detailed system modelling, but is also prone to the problem of state-space explosion. Schliecker et al (2010) proposed a method that employs a general event-based model to estimate the maximum load on a shared resource. This approach makes few assumptions about the task model and is thus quite generally applicable; however, it only supports a single unspecified work-conserving bus arbiter.…”

Section: Related Work With a Focus On The Memory Busmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Bounding the shared resource load for the performance analysis of multiprocessor systems

Cited by 51 publications

References 18 publications

Bounding memory interference delay in COTS-based multi-core systems

Bounding memory interference delay in COTS-based multi-core systems

Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters

An extensible framework for multicore response time analysis

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