Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters

Schranzhofer, Andreas; Pellizzoni, Rodolfo; Chen, Jian-Jia; Thiele, Lothar; Caccamo, Marco

doi:10.1109/rtas.2011.28

Cited by 43 publications

(33 citation statements)

References 15 publications

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“…Schranzhofer et al (2010) developed a framework based on a TDMA-arbitrated bus. This was followed by work on resource adaptive arbiters (Schranzhofer et al 2011). Their work assumes a task model where each task consists of sequences of super-blocks, themselves divided into phases that represent implicit communication (fetching or writing of data to/from memory), computation (processing the data), or both.…”

Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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“…e.g., [31]) consider the particular pattern of accesses that each contending task may make to the bus. Notably however, several of the latter type of works [33], [32] make assumptions that prevent their use in the two COTS processors considered in this paper. In particular, they model just one off-chip shared resource that can process one request at a time only and in which requests are synchronous (so that the contending task is stalled) and cannot be split into several asynchronous requests.…”

Section: Related Workmentioning

confidence: 99%

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Fernández

Abella

Quiñones

et al. 2015

2015 IEEE 18th International Symposium on Real-Time Distributed Computing

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Abstract-The timing verification of real-time singlecore systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes of the individual tasks, including the ETB, are studied from the system level perspective. The transition between those two steps involves accounting for the interference effects that arise when tasks contend for access to shared resource. The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress while actually holding the CPU, which are very difficult to tightly capture by simply inflating the tasks' ETB. In this paper we show how contention on access to hardware shared resources creates a circular dependence between the determination of tasks' ETB and their scheduling at run time. To help loosen this knot we present an approach that acknowledges different flavors of time composability, examining in detail the variant intended for partitioned scheduling, which we evaluate on two real processor boards used in the space domain.

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“…However, this turns to be rather complicated since it heavily depends on the dynamic task execution as well as the scheduling algorithm applied on the system. Prior work either assumes a specific memory access pattern [8] or a static cyclic scheduler [2], [4], however, these approaches suffer limitations when applying to the real applications.…”

Section: A Flow "Reshaping" By Throttlingmentioning

confidence: 99%

“…where N (t) is defined in Equation (4). Notice the α c (t) function is a step function and its upper bound α u c (t) is used to simplify the computation.…”

Section: A Static Budget Distributionmentioning

confidence: 99%

See 1 more Smart Citation

Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

Yun

Yao

Pellizzoni

et al. 2012

2012 24th Euromicro Conference on Real-Time Systems

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107

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Abstract-Shared resource access interference, particularly memory and system bus, is a big challenge in designing predictable real-time systems because its worst case behavior can significantly differ. In this paper, we propose a software based memory throttling mechanism to explicitly control the memory interference. We developed analytic solutions to compute proper throttling parameters that satisfy schedulability of critical tasks while minimize performance impact caused by throttling. We implemented the mechanism in Linux kernel and evaluated isolation guarantee and overall performance impact using a set of synthetic and real applications.

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Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters

Cited by 43 publications

References 15 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

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