Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

Yun, Heechul; Yao, Gang; Pellizzoni, Rodolfo; Caccamo, Marco; Sha, Lui

doi:10.1109/ecrts.2012.32

Cited by 105 publications

(58 citation statements)

References 20 publications

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“…access rate or distribution). It is possible to add this type of assumption, such as the specific memory access pattern of the tasks [9,5] or using memory request throttling mechanisms [44,10,43]. This will help us to calculate a tighter A p (t), while other equations in our work can be used independent of such additional assumptions.…”

Section: B Job-driven Bounding Approachmentioning

confidence: 99%

“…Previous studies on bounding memory interference delay [9,43,32,37,5] model main memory as a blackbox system, where each memory request takes a constant service time and memory requests from different cores are serviced in either Round-Robin (RR) or First-Come FirstServe (FCFS) order. This memory model, however, is not safe for commercial-off-the-shelf (COTS) multi-core systems because it hides critical details necessary to place an upper This material is based upon work funded and supported by the Department of Defense under Contract No.…”

Section: Introductionmentioning

confidence: 99%

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Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

171

158

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Abstract-In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. We explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, we analyze the worstcase memory interference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.

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Section: B Job-driven Bounding Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Bounding memory interference delay in COTS-based multi-core systems

Kim

Niz

Andersson

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

171

158

View full text Add to dashboard Cite

show abstract

“…This approach makes few assumptions about the task model and is thus quite generally applicable; however, it only supports a single unspecified work-conserving bus arbiter. Yun et al (2012) proposed a software-based memory throttling mechanism to explicitly limit the memory request rate of each core and thereby control the memory interference. They also developed analytical solutions to compute proper throttling parameters that ensure the schedulability of critical tasks while minimising the performance impact of throttling.…”

Section: Related Work With a Focus On The Memory Busmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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“…In our previous work, we investigated memory bandwidth reservation at the operating system level [21]. However, our existing solution has significant limitations.…”

Section: Introductionmentioning

confidence: 99%

“…Second, it can not adapt to dynamic changes in memory resource usage. Third, while the work in [21] provides safe performance guarantees for hard real-time tasks, it makes no effort to optimize memory throughput for soft real-time tasks, possibly resulting in severely reduced system performance. To address these limitations and challenges, we propose a new, efficient and fine-grained memory bandwidth management system, which we call MemGuard.…”

Section: Introductionmentioning

confidence: 99%

MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms

Yun

Yao

Pellizzoni

et al. 2013

2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-Memory bandwidth in modern multi-core platforms is highly variable for many reasons and is a big challenge in designing real-time systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efficient memory bandwidth reservation system, that we call MemGuard. MemGuard distinguishes memory bandwidth as two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efficient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core's reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput. I. INTRODUCTIONComputing systems are increasingly moving toward multicore platforms and their memory subsystem represents a crucial shared resource. As applications become more memory intensive and processors include more cores that share the same memory system, the performance of main memory becomes more critical for overall system performance.In a multi-core system, the processing time of a memory request is highly variable as it depends on the location of the access and the state of DRAM chips and the DRAM controller. There is inter-core dependency as the memory accesses from one core could also be influenced by requests from other cores; the DRAM controller commonly employs scheduling algorithms to re-order requests in order to maximize overall DRAM throughput [16]. All these factors affect the temporal predictability of memory intensive real-time applications due to the high variance of their memory access time. Therefore, there is an increasing need for memory bandwidth management solutions that provide Quality of Service (QoS).This problem has already been recognized by many researchers, and recent work has focused on designing more predictable memory controllers. For example, a reservation based approach has been applied to design a DRAM controller that supports real-time features [4]

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Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality

Cited by 105 publications

References 20 publications

Bounding memory interference delay in COTS-based multi-core systems

Bounding memory interference delay in COTS-based multi-core systems

An extensible framework for multicore response time analysis

MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms

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