MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms

Abstract

Abstract-Memory bandwidth in modern multi-core platforms is highly variable for many reasons and is a big challenge in designing real-time systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efficient memory bandwidth reservation system, that we call MemGuard. MemGuard distinguishes memory bandwidth as two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efficient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core's reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput. I. INTRODUCTIONComputing systems are increasingly moving toward multicore platforms and their memory subsystem represents a crucial shared resource. As applications become more memory intensive and processors include more cores that share the same memory system, the performance of main memory becomes more critical for overall system performance.In a multi-core system, the processing time of a memory request is highly variable as it depends on the location of the access and the state of DRAM chips and the DRAM controller. There is inter-core dependency as the memory accesses from one core could also be influenced by requests from other cores; the DRAM controller commonly employs scheduling algorithms to re-order requests in order to maximize overall DRAM throughput [16]. All these factors affect the temporal predictability of memory intensive real-time applications due to the high variance of their memory access time. Therefore, there is an increasing need for memory bandwidth management solutions that provide Quality of Service (QoS).This problem has already been recognized by many researchers, and recent work has focused on designing more predictable memory controllers. For example, a reservation based approach has been applied to design a DRAM controller that supports real-time features [4]

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A dynamic modelling framework for control-based computing system design

“…The first question addresses per-process memory limits, and could be used to achieve memory access temporal isolation [24]. The second question opens the door to transfers between swap and RAM that are time triggered instead of event triggered by process page faults.…”

Automated Fine-Grained CPU Provisioning for Virtual Machines

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