Board-level characterization of 1.0 and 1.27 mm pitch PBGA for automotive under-hood applications

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

“…When top and bottom dice sizes have the same length, larger die sizes of 5 · 5 mm is better than 3 · 3 mm, because the SED is more uniformly distributed in (2,2) and (4,4) balls. For 5 · 5 mm dice sizes, outermost (5,5) ball (see Fig. 6) also helps to share the load, therefore the performance is slightly better than control case with smaller top die size of 3.6 · 3.5 mm.…”

“…However, the process of thermal cycling test is time-consuming and costly. Therefore, FEA modeling [2][3][4][5][6][7][8][9][10][11][12][13] is widely used as an analysis tool for solder joint reliability, especially during the design stage of new package. There are many approaches used by researchers [14] in the modeling of fatigue life, e.g., stress-based, plastic/creep-based, energy-based, and damage accumulation-based.…”

Package and board level reliability modeling of advanced CSP pakages for telecommunication applications

“…Darveaux methodology [77][78][79] is a common approach used in the fatigue modeling which applies both energy and damage accumulation-based theories. Over the past few years, this model has been widely applied by many researchers [80][81]. In Darveaux's method, crack initiation life (N 0 ) and crack propagation life (N p ) are calculated:…”