Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Tee, Tong Yan; Zhong, Zhang

doi:10.1016/j.microrel.2004.04.019

Cited by 44 publications

(16 citation statements)

References 6 publications

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“…The die thickness used for this comparison is 0.25 mm. The relative trend of the effect of PCB thickness is similar as the results of TGBGA packages [30], QFN packages [31] and stack die BGA packages [32,32].…”

Section: Effect Of Pcb Thicknesssupporting

confidence: 72%

See 1 more Smart Citation

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Zhang

Kripesh

Chai

et al. 2008

Microelectronics Reliability

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Section: Effect Of Pcb Thicknesssupporting

confidence: 72%

“…Failure was defined as the number of cycles where the electrical resistance reading was above 300X. This value was used in other companies as well (e.g., ST Microelectronics [31][32][33]). The test standard followed is JESD22-A104-B, and the thermal profile used is À40°C to 125°C (42 min/cycle, 1 min ramp and 20 min dwell).…”

Section: Thermal Cycling Testmentioning

confidence: 99%

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Zhang

Kripesh

Chai

et al. 2008

Microelectronics Reliability

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“…Nowadays, the miniaturization levels required in the electronics industry has resulted in complex packaging solutions [15]. Therefore, the difficulty in imaging buried defects or flaws in complicated packaging schemes with multiple stacked devices has increased significantly [ Figure 1].…”

Section: Introductionmentioning

confidence: 99%

Magnetoresistive Sensors for Surface Scanning

Leitao¹,

Borme

Orozco

et al. 2013

Giant Magnetoresistance (GMR) Sensors

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Abstract. This chapter provides an overview on several techniques used for surface imaging, including SQUIDs, Hall-effect sensors, Giant magnetoimpedance sensors, and magnetoresistive (MR) sensors. Among all magnetic field sensors, only SQUIDs and MR devices have the potential to localize buried and non-visual field sources (such as defects in integrated circuits or magnetic field sources in biological environments. In particular, we describe how MR sensors have been used with advantage for integrated circuit (IC) mapping, with resolution below 500 nm and sensitivity to detect currents as low as 50 nA and have been used for many applications requiring low magnetic field detection. Challenges and experimental considerations on integration of MR sensors on a commercial analysis tool are provided here. Examples obtained with real devices demonstrate how Scanning Magnetic Microscopy has become an established failure analysis technique for visualizing current paths in microelectronic devices.

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“…However, the 3D-slice model can save much more time and storage under simulation analysis. In 2004, Tee et al [4] used a non-linear material to build a pyramid type BGA chip. According to the energy rule presented by Darveaux, the viscoplastic strain energy density was applied to deal with the calculations for the fatigue model.…”

Section: Introductionmentioning

confidence: 99%

Application of Optimal Design on Twin Die Stacked Package by Reliability Indicator of Average SED Concept

2012

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This paper deals with the optimal design for a twin die stacked package. Firstly, the numerical model is built up in terms of a three-dimensional slice model along the diagonal direction of the package. The material behavior of the solder balls is a consequence of the viscoplastic property which can be described by the Anand's model. Secondly, the Darveaux model is applied to predict the solder ball reliability of the stacked die package under a cyclic temperature loading. Since simulation analysis found an obvious relation is found between the fatigue life of the solder ball and the distribution of the accumulated strain energy density (SED) on the critical solder ball of the package through the simulation analysis, the average value of the strain energy density for all solder balls is adopted as the optimization indicator of reliability. With such a viewpoint, the critical solder ball position can be ignored, and accordingly an efficient analysis can be obtained. Finally, the Box-Behnken regression model is adopted to construct all the experiments. Each experiment analyzes the reliability of the package under varying parameters. Subsequently, the pattern search algorithm is applied to search for optimal factors.Through optimal analysis with the fatigue reliability indicator of an average SED, the fatigue life is found to be 59 lower than that of the original design. The fatigue life had clearly improved and the lowest ball fatigue life is found to be 2.859 times longer than the original one.

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Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Cited by 44 publications

References 6 publications

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

Magnetoresistive Sensors for Surface Scanning

Application of Optimal Design on Twin Die Stacked Package by Reliability Indicator of Average SED Concept

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