Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

Gal, Bertrand Le; Andriamisaina, Caaliph; Casseau, Emmanuel

doi:10.1109/socc.2006.283875

Cited by 11 publications

(14 citation statements)

References 6 publications

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“…Later work, however, has shown there to be little value in functional unit sharing in FPGA technology [9], owing to the high costs of implementing multiplexers in FPGAs. Other works include [10], which applied range analysis for bitwidth minimization in DSP circuits. [12] optimized bitwidth such that a limited amount of error is permitted in the generated hardware.…”

Section: B Bitwidth-aware High-level Synthesismentioning

confidence: 99%

Range and bitmask analysis for hardware optimization in high-level synthesis

Gort

Anderson

2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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We consider the extent to which the bit-level representation of variables can be used to optimize hardware generated by high-level synthesis (HLS). Two approaches to bit-level optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit hardware to be eliminated under certain conditions. Static compilerbased analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLSgenerated hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional optimizations based on dynamic analysis provide 34% area reduction.

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Section: B Bitwidth-aware High-level Synthesismentioning

confidence: 99%

Range and bitmask analysis for hardware optimization in high-level synthesis

Gort

Anderson

2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…2. The second one was proposed in [31] and assumes word-length unaware scheduling and binding tasks.…”

Section: Methodsmentioning

confidence: 99%

“…The scheduling and binding stages use the clusters previously identified to generate architectures with variable word-lengths. Multiple word-length approaches proposed in [31] and [32] are dedicated to pipeline scheduling. First approach [31] performs scheduling and binding without considering data-width information trying to minimize interconnection resource cost.…”

Section: High-level Synthesis With Variable Datapathmentioning

confidence: 99%

“…Multiple word-length approaches proposed in [31] and [32] are dedicated to pipeline scheduling. First approach [31] performs scheduling and binding without considering data-width information trying to minimize interconnection resource cost. Based on a data range analysis, resource word-length optimization is performed during the hardware architecture generation process taking into account data word-length (post-processing approach).…”

Section: High-level Synthesis With Variable Datapathmentioning

confidence: 99%

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Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Gal¹,

Casseau²

2010

J Sign Process Syst

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International audienceMultimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word- length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC

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“…The implementation bit-width Ω(n) considers the data coding, including sign extension named ψ(n) (if required) [13]. In order to optimally compute the size of each data manipulated by the application, the previously presented formal model is used to spread the dynamic range of the inputs to all the nodes of the graph.…”

Section: A Bit-width Analysismentioning

confidence: 99%

IP Generation Targeting Multiple Bit-Width Standards

Gal

Casseau

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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Multimedia applications such as video and image processing are computation intensive applications. For these applications the bit-width of data and operations is different all over the application. Generating optimized architectures is not an obvious task since it requires a deep bit-width analysis in order to properly size hardware resources. Furthermore implementing several application profiles onto the same chip makes it possible to avoid over-sized architectures or chip reconfiguration. In this paper we propose a design methodology based on high-level synthesis which takes into account multiple bit-width standards in order to generate area and power optimized architectures for embedded devices. First results demonstrate the interest of the approach.

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Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

Cited by 11 publications

References 6 publications

Range and bitmask analysis for hardware optimization in high-level synthesis

Range and bitmask analysis for hardware optimization in high-level synthesis

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

IP Generation Targeting Multiple Bit-Width Standards

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