Range and bitmask analysis for hardware optimization in high-level synthesis

Abstract

We consider the extent to which the bit-level representation of variables can be used to optimize hardware generated by high-level synthesis (HLS). Two approaches to bit-level optimization are considered (individually and together): 1) range analysis, and 2) bitmask analysis. Range analysis aims to predetermine min/max ranges for variables to reduce the bitwidth required to represent variables in hardware. Bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, where constants/don't-cares permit hardware to be eliminated under certain conditions. Static compilerbased analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLSgenerated hardware. For a set of benchmarks implemented in the Altera Cyclone II FPGA, results show bit-level optimizations in HLS based on static analysis reduce circuit area by 9%, on average, while additional optimizations based on dynamic analysis provide 34% area reduction.

Bitwidth-optimized hardware accelerators with software fallback

“…The work in [13] demonstrated an average area reduction of 9% using static range analysis, and a 34% area reduction with dynamic analysis. However, the dynamic analysis results in [13] are lower bound circuit areas, as the circuits are no longer correct for all inputs.…”

“…For example, a loop index i that ranges from 0 to 100 (specified as constant in the code) can be represented using 7 bits. Such ranges are then propagated forward and backward through the program's dataflow graph [13], [19], allowing ranges for other variables to be inferred. Bitwidth reductions made via static analysis preserve program correctness; the program will execute correctly for all input datasets.…”

“…The recent release of LegUp HLS (ver. 3.0) includes both static and dynamic range analysis [13], which we leverage in our research. Note that while we choose to use the static and dynamic analysis algorithms implemented by [13], our work is orthogonal to the particular bitwidth minimization approach used.…”

“…However, the dynamic analysis results in [13] are lower bound circuit areas, as the circuits are no longer correct for all inputs. Our work aims to provide most of the area-reduction benefits of dynamic range analysis, while retaining functional correctness.…”

“…The profiled variable ranges are passed to a compiler-based range analysis tool [13], which propagates values forward and backward through the program's dataflow graph, potentially reducing variable ranges further. Next, we modify the program's intermediate representation (assembly code) to add input-checking functionality to the accelerator, consisting of comparing the run-time values of variables with their common-case ranges determined from profiling.…”