Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Gal, Bertrand Le; Casseau, Emmanuel

doi:10.1007/s11265-010-0467-8

Cited by 10 publications

(1 citation statement)

References 30 publications

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“…Le Gal et al [22], Constantinides et al [21] and Menard et al combined the word length optimisation and high‐level synthesis (HLS) problems. These works propose new HLS methodologies which take care of data word length in scheduling, allocation and binding processes to aim at optimising the hardware implementation.…”

Section: Related Workmentioning

confidence: 99%

Accuracy‐aware processor customisation for fixed‐point arithmetic

Vakili¹,

Langlois²,

Bois³

2016

IET Computers & Digital Techniques

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Section: Related Workmentioning

confidence: 99%

Accuracy‐aware processor customisation for fixed‐point arithmetic

Vakili¹,

Langlois²,

Bois³

2016

IET Computers & Digital Techniques

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Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter

Bhattacharya

Kumar

Biswas

2017

Circuit Theory & Apps

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Summary This paper presents a semi‐automated word‐length optimization framework to reduce field‐programmable gate array (FPGA) resource utilization for FPGA‐based pre‐silicon test emulation of analog and mixed signal circuits while achieving the desired accuracy and overcoming long optimization time. Although high‐level behavioral models exist for modeling analog and mixed signal circuits, these comprise many complex differential equations which cannot be realized implicitly using Boolean logic (which is the basic functional block of an FPGA) on an FPGA. So, a more convenient way is explored to map analog circuits into digital domain by converting them into fixed‐point architectures because of its advantage of manipulating data with lower word‐length. To address the loss of accuracy due to finite word‐length effects and limited reconfigurable resources, word‐lengths are optimized under the constraint of given performance metrics. The proposed technique built in MATLAB/Simulink environment with Xilinx System Generator support is illustrated with the help of a case study of a peak‐current‐mode‐controlled buck‐type switching converter implemented on Xilinx Virtex™‐5 FPGA. To illustrate the applicability of this environment for pre‐silicon test development, well‐accepted fault models are emulated with the help of non‐ideal model of a buck converter. The emulation results are seen to be close to that of a post‐fabricated power converter in the presence of faults. Experimental results show that FPGA resource utilization can be reduced significantly while achieving the desired performance accuracy under the constraint of multiple error metrics. Copyright © 2017 John Wiley & Sons, Ltd.

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An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules

Atitallah

Kammoun

Ali

et al. 2020

Circuit Theory & Apps

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SummaryTwo main design methods are currently widely adopted in dealing with complex signal processing algorithms. The first method is based on low‐level synthesis (LLS), which consists in writing the hardware description languages (HDL) code manually. However, the second method, called high‐level synthesis (HLS), generates the register transfer level (RTL) description automatically starting from a high‐level description language. The challenge in this paper was to study the impact of both design methods on such a complex application as the High Efficiency Video Coding (HEVC) decoder. With this end in view, we analyzed the complexity of the HEVC decoder in a software environment using version 10 of the HEVC test model (HM) reference software to determine which portions tended to get optimized. The combined architecture for the intra prediction (IP) and the inverse quantization and transform (IQ/IT) was then implemented in hardware using HLS and LLS. The findings obtained under the Xilinx Zynq 7045‐based field‐programmable gate array (FPGA) proved that the HLS implementation enabled a gain of about 80% in Look Up Table (LUTs) with an increase of 93% in DSP blocks compared with LLS implementation. Yet only the LLS solution could achieve the real‐time decoding of 4K@26fps instead of the 1080p@24fps by the HLS design.

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Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Cited by 10 publications

References 30 publications

Accuracy‐aware processor customisation for fixed‐point arithmetic

Accuracy‐aware processor customisation for fixed‐point arithmetic

Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter

An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules

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