Bias temperature instability in High-&amp;#x03BA;/metal gate transistors - Gate stack scaling trends

Krishnan, Siddarth; Narayanan, V.; Cartier, E.; Ioannou, D.P.; Zhao, Kai; Ando, Takashi; Kwon, U.; Linder, B.; Stathis, J. H.; Chudzik, M.; Kerber, A.; Choi, Kwang-Il

doi:10.1109/irps.2012.6241838

Cited by 20 publications

(13 citation statements)

References 9 publications

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“…As shown in Figure 6(b) , thicker SiO 2 IL results in less Δ V th, which is also in agreement with [ 6 ]. The less Δ V th observed in thicker SiO 2 IL can be attributed to smaller fast transient charging effect, which is similarly reported in other studies [ 6 , 28 ]. According to [ 13 ], the thinner SiO 2 IL experiences higher gate oxide field, thereby accelerating the NBTI degradation effect because of the subsequent increase of the diffusion rate of hydrogen species.…”

Section: Simulation Resultssupporting

confidence: 86%

Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Hussin

Soin

Bukhori

et al. 2014

The Scientific World Journal

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We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

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Section: Simulation Resultssupporting

confidence: 86%

Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Hussin

Soin

Bukhori

et al. 2014

The Scientific World Journal

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“…The Bias Temperature Instability (BTI) is considered a major reliability concern in nano-scale CMOS technologies [12]. It is classified into Negative Bias Temperature instability (NBTI) and Positive Bias Temperature Instability (PBTI) [13].…”

Section: Nbti Sensitivity Analysismentioning

confidence: 99%

“…Negative Bias Temperature Instability (NBTI) is another important reliability concern resulting in V th increase for PMOS transistors over life-time and hence impacting circuit power, performance, and reliability [12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Kuttappa

Homayoun

Salmani

et al. 2016

Microelectronics Reliability

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Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm bulk CMOS, for the same total device area, the voltage sensing scheme offers 17% to 28% lower failure rates under combined intra-die transistor and MTJ variations, comparable delay, and 56% lower active power compared to the current sensing scheme. Moreover, we compare the reliability of the two sensing schemes under Negative Bias Temperature Instability (NBTI) of PMOS transistors. Our results indicate that the failures rates increase over time by transistor aging for both designs, and the voltage sensing scheme maintains its improved failure rate over to the current sensing scheme.

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“…However, the reliability of transistors with high-j gate dielectric is a crucial issue because of the poor high-j/Si interface and trap states in the high-j film [12,13]. Therefore, the negative and positive bias temperature instabilities (N/PBTI) are very important for the development of CMOS transistors with high-j gate dielectric [14]. Nevertheless, the NBTI behavior of p-type LTPSTFTs and the PBTI behavior of n-type LTPS-TFTs with high-j gate dielectric have not been simultaneously studied and compared.…”

Section: Introductionmentioning

confidence: 99%

Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

Cheng-Yu

Huang

2015

Solid-State Electronics

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Bias temperature instability in High-κ/metal gate transistors - Gate stack scaling trends

Cited by 20 publications

References 9 publications

Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Bias temperature instability comparison of CMOS LTPS-TFTs with HfO2 gate dielectric

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