Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Abstract

Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor and MTJ variations in nano-scale. The sources of process variations include both the CMOS device related variations and the MTJ variations. A key part of the STT based LUTs is the sense amplifier needed for reading out the MTJ state. We compare the voltage and current based sensing schemes in terms of the power, performance, and reliability metrics. Based on our simulation results in a 16nm bulk CMOS, for the same total device area, the voltage sensing scheme offers 17% to 28% lower failure rates under combined intra-die transistor and MTJ variations, comparable delay, and 56% lower active power compared to the current sensing scheme. Moreover, we compare the reliability of the two sensing schemes under Negative Bias Temperature Instability (NBTI) of PMOS transistors. Our results indicate that the failures rates increase over time by transistor aging for both designs, and the voltage sensing scheme maintains its improved failure rate over to the current sensing scheme.

A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM

“…Then, the V th shift caused by the NBTI can be recovered, and the pMOS transistor is put into recovery mode [22]. According to several NBTI models proposed in references [24,25,26,27], the V th degradation is highly dependent on stress voltage (V SG ) and stress time (t). A NBTI model based on trapping/de-trapping theory under two voltages cycle to cycle are described by Eq.…”

NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-basedlook-up table for ultralow power and highly reliable FPGA designs

“…It is generally composed of three components: 1) a sense amplifier (SA) to read a selected MTJ cell in the STT-LUT and produce full swing output voltage; 2) a selection tree with volatile logic data to choose a unique MTJ cell; 3) a write circuit to program the input data in a selected MTJ cell. In this design, the MTJ cells are directly connected to the selection tree circuit and the sense amplifier is shared among them [15][16][17][18][19][20][21].…”

“…Different STT-LUT circuits have already been proposed in the literature (e.g., [15][16][17][18][19][20][21][22][23][24]). However, they suffer from long read delays and less reliability (due to such failures as decision failure, write failure, and read disturb).…”

“…However, the critical issues in SRAM-based FPGA devices are the increasing leakage currents in the configuration memory and vulnerability against particle strikes. The integration of STTRAM in FPGA instead of SRAM is one of the most promising solutions to overcome these issues [15][16][17][18][19][20][21][22][23]. Spin-torque transfer random access memory (STTRAM) is a promising memory technology for high-density on-chip caches due to its low leakage power and robustness against particle strikes.…”