Benchmarking the performance of ultrathin body InAs-on-insulator transistors as a function of body thickness

Abstract

The effect of body thickness (5-13 nm) on the leakage currents of top-gated, InAs-on-insulator field-effect-transistors with a channel length of ∼200 nm is explored. From a combination of experiments and simulation, it is found that the OFF-state currents are primarily dominated by Shockley Read Hall recombination/generation and trap-assisted tunneling. The OFF currents are shown to decrease with thickness reduction, highlighting the importance of the ultrathin body device configuration. The devices exhibit promising performances, with a peak extrinsic and intrinsic transconductances of ∼1.7 and 2.3 mS/μm, respectively, at a low source/drain voltage of 0.5 V and a body thickness of ∼13 nm.

Ultrathin-Body High-Mobility InAsSb-on-Insulator Field-Effect Transistors

“…The source contact resistance R S of the 7-nm-thick InAsSb was extracted using the transmission line method. The extracted R S is ∼200 Ω · μm, which is close to that of the 8-nm InAs FETs (∼230 Ω · μm) [16].…”

“…As shown in Fig. 4(a) and (b), a 7-nm-thick InAsSb FET (L G = 500 nm) exhibits I ON /I OFF ∼ 2 × 10 2 when defining I OFF at V T − 1/3V DD and I ON at V T + 2/3V DD at room temperature (V T is taken at I = 10 −6 A/μm) and exhibits an I ON of ∼0.38 mA/μm at V DS = V GS = 0.6 V. A subthreshold swing of SS ∼ 178 mV/dec is obtained, which is larger than that of InAs FETs (SS ∼ 125 mV/dec) [16]. This suggests that the InAsSb interfaces exhibit a higher density of trap states than InAs.…”

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

“…Based on the data presented in this paper we draw some general conclusions regarding III-V NWs and their implementation; although high intrinsic performance, that is high transconductance and drive currents, has been demonstrated in various forms of III-V nanowires [4] [14][15] [16], it is clear that the implementation of RFcompatible devices still is a challenge. Analysis of planar III-V MOSFETs [23] show that the control of the access resistance is one of the key parameters to increase the transconductance and to obtain attractive RF-properties.…”

“…Quantifying g m,peak -widths, the values for s-FETs and a-FETs do not differ, suggesting there is not a significant spread in V T within arrays that would cause a degraded maximum g m . For reference, we have benchmarked our data with other high performance InAs and InGaAs NW FETs; a 13 nm planar XOI FET, L G = 230 nm [14], a 25 nm diameter InAs/InP radial nanowire FET (Ω-gate, I DS,norm = I DS /(n·0.75π·D NW )), L G = 170 nm [15], a 15 nm in diameter lateral NW, L G = 100 [4], and a top down rectangular GGA FET (20x30 nm), L G = 20 nm [16].…”

An InAs/high-k/low-k structure: Electron transport and interface analysis

“…8,9 In particular, heterogeneous integration of InAs devices on foreign host substrates is quite important. [10][11][12][13] We previously fabricated and investigated an InAs/low-k structure, where high-quality InAs thin films are bonded on host low-dielectric-constant (low-k) flexible substrates (FS), [14][15][16][17] by using epitaxial liftoff (ELO) and van der Waals bonding (VWB) method. 18,19 The InAs/low-k (InAs/FS) exhibits high electron mobilities, where the FS with k ∼ 3, polyethylene terephthalate (PET) coated by bisaziderubber, has a merit for device applications because of a low parasitic capacitance.…”