Benchmarking of Hardware Trojans and Maliciously Affected Circuits

Shakya, Bicky; He, Xue-Zhong; Salmani, Hassan; Forte, Domenic; Bhunia, Swarup; Tehranipoor, Mark

doi:10.1007/s41635-017-0001-6

Cited by 234 publications

(121 citation statements)

References 36 publications

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“…Trojans also come in a wide variety of formats so no single filter can catch them all. These Trojans are unwanted and pose a risk to the chip owners of receiving secretly modified hardware that could lead to devastating consequences [1], [2]. A hardware Trojan can be classified into three main categories according to their physical, activation, and action characteristics [1], [2].…”

Section: Background and Experimental Set-up A Hardware Trojan Anmentioning

confidence: 99%

“…While the transition from vertically integrated supply chains to horizontally integrated has decreased costs for integrated circuit (IC) designers; the "fabless" approach comes with the steep price of trust [1], [2], [4]- [6], [8]- [11]. Semiconductor designers now must trust their intellectual property (IP) to multiple parties in order to have their ICs manufactured at foundries [8], [11].…”

Section: Introductionmentioning

confidence: 99%

“…Semiconductor designers now must trust their intellectual property (IP) to multiple parties in order to have their ICs manufactured at foundries [8], [11]. Not only do they run the risk of having their IP stolen, but it is not uncommon for untrusted system integrators and foundries to insert hardware Trojans before shipping the final product [1], [2], [4], [5]. These Trojans are capable of leaking sensitive information, disabling key portions of the IC, self-destructing the chip, or hindering performance [1], [2].…”

Section: Introductionmentioning

confidence: 99%

“…Not only do they run the risk of having their IP stolen, but it is not uncommon for untrusted system integrators and foundries to insert hardware Trojans before shipping the final product [1], [2], [4], [5]. These Trojans are capable of leaking sensitive information, disabling key portions of the IC, self-destructing the chip, or hindering performance [1], [2]. This has driven the need for fast, accurate, and simple methods of detecting infected ICs before they are able to taint the supply chain.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Supervised Machine Learning Techniques for Trojan Detection with Ring Oscillator Network

Worley

Rahman

2019

2019 SoutheastCon

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With the globalization of the semiconductor manufacturing process, electronic devices are powerless against malicious modification of hardware in the supply chain. The everincreasing threat of hardware Trojan attacks against integrated circuits has spurred a need for accurate and efficient detection methods. Ring oscillator network (RON) is used to detect the Trojan by capturing the difference in power consumption; the power consumption of a Trojan-free circuit is different from the Trojan-inserted circuit. However, the process variation and measurement noise are the major obstacles to detect hardware Trojan with high accuracy. In this paper, we quantitatively compare four supervised machine learning algorithms and classifier optimization strategies for maximizing accuracy and minimizing the false positive rate (FPR). These supervised learning techniques show an improved false positive rate compared to principal component analysis (PCA) and convex hull classification by nearly 40% while maintaining > 90% binary classification accuracy.

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Section: Background and Experimental Set-up A Hardware Trojan Anmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Supervised Machine Learning Techniques for Trojan Detection with Ring Oscillator Network

Worley

Rahman

2019

2019 SoutheastCon

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“…A good survey of all these methods can be found at [4] and [5]. Most of the work in this area make use of a popular open-source benchmark suite to validate their methods [1], and an extended work of the trust-hub can be found at [2]. The trust-hub [6] contains a variety of designs with Hardware Trojan classified in different domains (i.e., insertion phase, activation mechanism, effect).…”

Section: Introductionmentioning

confidence: 99%

S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis

Veeranna

Schafer

2017

J Hardw Syst Secur

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This work presents an open-source benchmark suite of synthesizable behavioral descriptions with different types of hardware Trojan. A repository of RT-level benchmarks with different types of Hardware Trojan is available at the Trust-hub (https://www.trust-hub.org/resources/ benchmarks). Unfortunately, this benchmark suite misses completely the behavioral abstraction level. This work aims at bridging this gap by providing the first behavioral synthesis benchmark suite in a common language supported by all major HLS vendors (SystemC) which cover most of the hardware Trojan types. The designs have been created in such a way that the hardware Trojan cannot be found using standard software profiling techniques (i.e., 100% code coverage in most of the cases). This work also presents the obfuscated version of the benchmarks which makes it even hard to detect the hardware Trojans using the traditional verification approaches.

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Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

Abed

Mohd

Hayajneh

et al. 2021

Circuit Theory & Apps

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Summary Hardware Trojans (HTs) are malicious and intentional modification of the hardware design, embedded by an adversary to leak sensitive data, modify functionality, or cause malfunction. Lightweight ciphers are designed for resource‐constrained devices (RCDs) to balance resources and security, but often targeted by HTs. This work aims to create a trusted lightweight cipher design and detect complex sequential HTs using a runtime monitoring method with minimal resource overhead. The novelty of the approach is that it combines full or partial temporal redundancy, resource minimization, and runtime monitoring. The algorithm employs temporal redundancy, by executing a first run of the cipher, and then replays the cipher fully (ReplayN method) or partially (ReplayN/2 method). A mismatch indicates HT activity, and a third replay is executed to determine the correct results. The ReplayN/2 algorithm further optimizes time and energy by limiting replay to the second half of the cipher rounds. The proposed method is compared with other existing methods including triple modular redundancy (TMR), adapted triple modular redundancy (ATMR), and reverse‐function redundancy (RFR). All methods were implemented in field‐programmable gate array (FPGA) technology. Implementation performance metrics were measured and compared, including resource utilization (i.e., logical elements [LEs]), power, energy (E), and speed (i.e., Fmax). The results show that the proposed algorithm outperforms existing methods in most of the metrics. In terms of speed and area, the replay algorithm is faster by 24% and reduces total LEs by 42% when compared with existing methods. Regarding power, replay algorithm reduces power by 45% when compared with TMR and ATMR. With respect to energy, replay methods reduce energy by an average of 6% when compared with TMR and ATMR. The ReplayN/2 reduces energy by an average 15% when compared with TMR and ATMR. Based on the normalE×LE (i.e., energy × area) metric, ReplayN/2 is the top performing method as it balances area and energy metrics. Using normalE×LEnormalFmax metric, the replay methods are the best performing methods as they best balance area, energy, and speed. Also, based on ThroughputLE2 metric, the replay methods are the top performing methods.

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Benchmarking of Hardware Trojans and Maliciously Affected Circuits

Cited by 234 publications

References 36 publications

Supervised Machine Learning Techniques for Trojan Detection with Ring Oscillator Network

Supervised Machine Learning Techniques for Trojan Detection with Ring Oscillator Network

S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

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