Backend CAD flows for "restrictive design rules"

Abstract

To meet challenges of d e e p subwavelength technologies (particularly 130nm and following), Lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETS like altPSM. For emerging technologies (65nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the Design->Silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. ing how Design might take advantage of these restrictions, and will present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPCmET algorithms and the accuracy of models of manufactured products. ing technology, including simulation and analysis, may be applicable to a variety of approaches to Design For ManufacturabilityWe have been explorWe also believe that the underly-(DFM).

Power-Gating for Leakage Control and Beyond

“…Several design methodologies have been proposed in the last years, from those based on Design for Manufacturability approaches [13,18,25] (like litho-friendly and Restricted Design Rules layout design), where variability of a given design is either mitigated or amortized, to Adaptive strategies, which attempt to solve the variability issues by sensing and correcting the desired parameters using various knobs that affect them. These schemes are also called Monitor & Control (M&C) strategies, to emphasize their analogy with closed-loop control systems.…”

Characterization and design for variability and reliability

“…Many of the layout dependent effects can be minimized by restrictive design rules (RDRs) [17,18] and optical proximity correction (OPC) [19,20] techniques. However, in spite of RDRs and OPC, a large set of layout configurations can still cause a significant systematic shift in the device parameters.…”

“…A design methodology called L3GO (Layout using Gridded Glyph Geometry Objects) [18] was developed to implement RDRs and exploit regularity. In the L3GO approach, layout is performed using glyphs instead of shapes.…”

Yield Analysis and Optimization

“…To cope with sub-100nm manufacturability concerns where manufacturing equipment is not keeping pace with feature scaling, radically restraining layout options has been proposed as a viable option [46,45]. One common restriction is to enforce regularity in layout which aids printability.…”