No abstract

No abstract

To meet challenges of d e e p subwavelength technologies (particularly 130nm and following), Lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETS like altPSM. For emerging technologies (65nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the Design->Silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. ing how Design might take advantage of these restrictions, and will present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPCmET algorithms and the accuracy of models of manufactured products. ing technology, including simulation and analysis, may be applicable to a variety of approaches to Design For ManufacturabilityWe have been explorWe also believe that the underly-(DFM).

No abstract

No abstract