Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions

Alizadeh, Bijan; Fujita, Masahiro

doi:10.1007/978-3-540-75596-8_11

Cited by 10 publications

(2 citation statements)

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“…Verification approaches for bit-vector arithmetic such as term-rewriting, arithmetic decision procedures, polynomial decision diagrams and word-level ATPG have been studied in [9]- [11]. The authors in [11] have used integer arithmetic in constraint satisfaction for ILP-based simulation vector generation.…”

Section: Related Workmentioning

confidence: 99%

A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Alizadeh

Fujita

2009

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gatelevel implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z 2 n . The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.

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Section: Related Workmentioning

confidence: 99%

A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Alizadeh

Fujita

2009

IEICE Trans. Inf. & Syst.

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“…Various optimizations were proposed to reduce the verification problem. One optimization approach to reduce the size of the problem instance, is to extend the verification algorithm by cutpoint detection [8], [9], [10]. Cutpoints represent parts within two designs (e.g., the specification and the implementation) which are functionally equivalent.…”

Section: Introductionmentioning

confidence: 99%

Debugging HDL designs based on functional equivalences with high-level specifications

Finder

Witte

Fey

2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-The increasing complexity of circuits and systems is forcing design specifications to software-like programming languages like C. Since the conversion from software to hardware is a difficult task solved manually, bugs are frequently introduced in the HDL design. Sophisticated automated error localization and correction techniques, i.e. debugging, are a challenge.In this paper a new automated method is presented for debugging hardware implementations when a software-like specification in C is given. Based on functional equivalences between software and hardware, error localization and correction are automated. We present experimental results for different types of designs and different types of faults.

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Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker

Bandyopadhyay

Banerjee

Sarkar

et al. 2012

Progress in VLSI Design and Test

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Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions

Cited by 10 publications

References 10 publications

A Unified Framework for Equivalence Verification of Datapath Oriented Applications

A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Debugging HDL designs based on functional equivalences with high-level specifications

Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker

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