Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker

Bandyopadhyay, Sambaran; Banerjee, Kunal; Sarkar, Dipankar; Mandal, Chittaranjan

doi:10.1007/978-3-642-31494-0_9

Cited by 7 publications

(1 citation statement)

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“…The method of Karfa et al and Kundu, Lerner, and Gupta can be applied for checking equivalence of programs where instruction‐level parallelism is applied. Bandyopadhyay et al have proposed a path‐based method for checking equivalence between a sequential scalar program and its transformed parallel version using PRES+ model for verification of thread‐level parallelization technique. An approach to prove correctness of parallelizing compilers is proposed, and a notion of bisimulation equivalence technique between a sequential source program and thread‐level parallel program is implemented using a theorem prover in the study of Hu and Hutton .…”

Section: Background and Motivationmentioning

confidence: 99%

Validation of parallelizing transformations of sequential programs

Dutta

2017

Concurrency and Computation

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Summary Transformations for high‐performance superscalar, vector, and parallel processors maximize parallelism and memory locality. Often parallelizing compilers apply transformations, such as loop parallelization and loop vectorization, to convert a sequential array‐handling program into a parallel program. Validation of such transformations is extremely useful in the prevalent high‐performance computing environment. This paper proposes a novel algorithm for construction of the dependence graph of the generated parallel programs. These transformations are validated by checking equivalence of the dependence graphs of the original sequential program and the transformed parallel program using a standard algorithm reported in the literature. The above equivalence checker works even when the above parallelizing transformations are preceded by various enabling transformations except for loop collapsing transformation that changes the dimensions of the arrays. In the present paper, the scope of the equivalence checker has been expanded to handle this special case by informing it of the correspondence between the index spaces of the corresponding of input and output arrays in the sequential and the parallel programs. The proposed methods are implemented and tested against a set of available benchmark programs that are parallelized by the polyhedral auto‐parallelizer LooPo and the auto‐vectorizer Scout.

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Section: Background and Motivationmentioning

confidence: 99%