A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Abstract

SUMMARYIn this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gatelevel implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z 2 n . The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.

A dynamic specification to automatically debug and correct various divider circuits

“…For example in Fig. 14(a) the highlighted node that is labeled as SCQC is the node that in this step is determined as output of CPL (i.e., Gate 7,8,9,10,and 11). Based on the CPL extraction FBLA will be updated as is shown in Fig.…”

“…A well-known approach in verifying arithmetic circuits is to extract arithmetic operations from the gate-level implementation and then generate an arithmetic model to be compared with a high level specification [5] [10]. For example this technique can check the equivalence of integer multipliers based on a bit level reverse-engineering approach.…”

“…As the number of possible architectures for a multiplier is limited one may incorporate a variety of architectures in the frontend of the equivalence checker and repeat the comparison for all of them. The verification approach in [5] [10] benefits from an efficient reverse-engineering process in extracting a network of half-adders from the gate-level circuit, while there is no need of an exhaustive process to map carry signals.…”

“…Although these techniques seem to be robust for large arithmetic circuits, they are not able to handle dividers. One of our contributions in this paper is extending the debugging technique in [5] [10] in order to verify and debug large arithmetic systems that contain dividers in addition to adders and multipliers.…”

“… Dynamically representing the specification that can extend our proposed debugging algorithm in such a way that can be applied to optimized arithmetic circuits while the techniques in [5] [10] are not able to handle such designs, as will be discussed in Section V.  Formally describing a wide range of arithmetic circuits including fast array dividers as well as sequential dividers by proposing functional bit-level and logical bit-level representations while the technique in [23] is just applicable to restoring and non-restoring dividers.  Showing empirical results to prove that our proposed debugging technique enables us to verify and debug large industrial arithmetic circuits within practical time.…”