A formal approach to debug polynomial datapath designs

Alizadeh, Bijan

doi:10.1109/aspdac.2012.6165043

Cited by 10 publications

(4 citation statements)

References 26 publications

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“…In [29], we have performed such division process by using a canonical word-level decision diagram called Horner Expansion Diagram (HED) [14,15]. As explained in Section 3.3, the HED is a binary graph-based representation which is able to represent polynomial function by factorizing variables recursively.…”

Section: Improving Groebner Basis Reductionmentioning

confidence: 99%

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Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Farahmandi

Alizadeh

2015

Microprocessors and Microsystems

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Section: Improving Groebner Basis Reductionmentioning

confidence: 99%

“…In Section 3 we briefly describe some mathematical background as well as Horner Expansion Diagrams (HEDs) [14,15]. Section 4 presents our proposed verification technique in detail.…”

Section: Introductionmentioning

confidence: 99%

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Farahmandi

Alizadeh

2015

Microprocessors and Microsystems

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“…The HED is a binary graph-based representation which is able to represent polynomial function by factorizing variables recursively as shown in (1), where const is a term which is independent of variable y, while linear is another term which is served as the coefficient of variable y [15]. x If v C (is a Constant node), then f v = val(v).…”

Section: B Improving Polynomial Reduction Phase Using Hedmentioning

confidence: 99%

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits

Farahmandi

Alizadeh

Navabi

2014

2014 IEEE Computer Society Annual Symposium on VLSI

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Arithmetic circuits require a verification process to prove that the gate level circuit is functionally equivalent to a high level specification. This paper presents an automatic equivalence checking technique to verify combinational arithmetic circuits at bit level. In order to efficiently verify gate level arithmetic circuits, we make use of computer algebra based approach so that the circuit and the specification are modeled in polynomial system and the verification problem is formulated as polynomial reduction techniques using Groebner basis of circuit polynomial corresponding ideal. To overcome costly Groebner basis computation as well as intensive polynomial reduction, we make use of a canonical decision diagram named Horner Expansion Diagram (HED), derive a suitable term order to represent and manipulate polynomials efficiently and find repetitive components based on automata. To evaluate the effectiveness of our verification technique, we have applied it to very large arithmetic circuits including multipliers. Preliminary experimental results show that the proposed verification technique is scalable enough so that large multipliers can efficiently be verified in reasonable run time and memory usage.

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“…A Large amount of work has been done in this area, however, many of them just output a list of error locations without attempting to automatically correct them [1,2]. Recently, a mutation-based debugging technique for diagnosis and correction of datapath-dominated applications has been proposed [3]. But this technique is not efficient in the case of multiple errors, because it needs to exhaustively check all possible changes in a design in order to automatically correct them.…”

Section: Introductionmentioning

confidence: 99%

Automatic correction of certain design errors using mutation technique

Behnam

Alizadeh

Navabi

2014

2014 19th IEEE European Test Symposium (ETS)

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In this paper, we introduce a new technique that makes use of satisfiability (SAT) based debugging techniques along with a mutation-based technique to correct certain design errors in digital designs automatically. The experimental results demonstrate that our proposed method enables us to locate and correct multiple bugs by targeting gate replacements and wire exchanging within reasonable run-time and memory usage for several designs.

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A formal approach to debug polynomial datapath designs

Cited by 10 publications

References 26 publications

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits

Automatic correction of certain design errors using mutation technique

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