Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Farahmandi, Farimah; Alizadeh, Bijan

doi:10.1016/j.micpro.2015.01.007

Cited by 39 publications

(15 citation statements)

References 29 publications

(66 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The most advanced techniques that have potential to solve the arithmetic verification problems are those based on Symbolic Computer Algebra. The verification problem is typically formulated as a proof that the implementation satisfies the specification [2] [1] [8] [7] [9]. This is accomplished by performing a series of divisions of the specification polynomial F by a set of implementation polynomials B, representing circuit components, the process referred to as reduction of F modulo B. Polynomials f 1 , ..., f s ∈ B are called the bases, or generators, of the ideal J.…”

Section: Computer Algebra Approachesmentioning

confidence: 99%

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Ciesielski

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Galois field (GF) arithmetic circuits find numerous applications in communications, signal processing, and security engineering. Formal verification techniques of GF circuits are scarce and limited to circuits with known bit positions of the primary inputs and outputs. They also require knowledge of the irreducible polynomial P (x), which affects final hardware implementation. This paper presents a computer algebra technique that performs verification and reverse engineering of GF(2 m ) multipliers directly from the gate-level implementation. The approach is based on extracting a unique irreducible polynomial in a parallel fashion and proceeds in three steps: 1) determine the bit position of the output bits; 2) determine the bit position of the input bits; and 3) extract the irreducible polynomial used in the design. We demonstrate that this method is able to reverse engineer GF(2 m ) multipliers in m threads. Experiments performed on synthesized Mastrovito and Montgomery multipliers with different P (x), including NIST-recommended polynomials, demonstrate high efficiency of the proposed method.

show abstract

Section: Computer Algebra Approachesmentioning

confidence: 99%

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Ciesielski

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…, xn]/2 N up to 128 bit can be efficiently performed using this method. An extension of this method has been presented in [13] that is able to significantly reduce the number of polynomials by finding fanout-free regions and representing the whole region by one single polynomial. Similar to [27], the reduction of specification polynomial with respect to Gröbner basis polynomials is performed by Gaussian elimination resulting in verification time of few minutes.…”

Section: Figure 4: Equivalence Checking Using Sat Solversmentioning

confidence: 99%

Pre-silicon security verification and validation

Guo

Dutta

Jin

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

Self Cite

View full text Add to dashboard Cite

Reusable hardware Intellectual Property (IP) based Systemon-Chip (SoC) design has emerged as a pervasive design practice in the industry today. The possibility of hardware Trojans and/or design backdoors hiding in the IP cores has raised security concerns. As existing functional testing methods fall short in detecting unspecified (often malicious) logic, formal methods have emerged as an alternative for validation of trustworthiness of IP cores. Toward this direction, we discuss two main categories of formal methods used in hardware trust evaluation: theorem proving and equivalence checking. Specifically, proof-carrying hardware (PCH) and its applications are introduced in detail, in which we demonstrate the use of theorem proving methods for providing high-level protection of IP cores. We also outline the use of symbolic algebra in equivalence checking, to ensure that the hardware implementation is equivalent to its design specification, thus leaving little space for malicious logic insertion.

show abstract

“…The work in [7] improves the scalability by rewriting the polynomial model of the circuit, making the verification of a limited class of integer multipliers feasible. The technique This work was supported in part by the German Research Foundation (DFG) within the Reinhart Koselleck project DR 287/23-1, by the University of Bremen's graduate school SyDe, funded by the German Excellence Initiative and by the German Federal Ministry of Education and Research (BMBF) within the project EffektiV under contract no.…”

Section: Introductionmentioning

confidence: 99%

“…The main reason-as identified by us-is the accumulation of vanishing monomials, which refers to monomials that always evaluate to zero. The problem is that these vanishing monomials cannot be identified locally using the approach of [7].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction

Sayed-Ahmed

Große

Kühne

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Formal verification utilizing symbolic computer algebra has demonstrated the ability to formally verify large Galois field arithmetic circuits and basic architectures of integer arithmetic circuits. The technique models the circuit as Gröbner basis polynomials and reduces the polynomial equation of the circuit specification wrt. the polynomials model. However, during the Gröbner basis reduction, the technique suffers from exponential blow-up in the size of the polynomials, if it is applied on parallel adders and recoded multipliers. In this paper, we address the reasons of this blow-up and present an approach that allows to apply the technique on basic and complex parallel architectures of multipliers. The approach is based on applying a logic reduction rule during Gröbner basis rewriting. The rule uses structural circuit information to remove terms that evaluate to zero before their blow-up. The experiments show that the approach is applicable up to 128 bit multipliers.

show abstract

Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction

Cited by 39 publications

References 29 publications

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering

Pre-silicon security verification and validation

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction

Contact Info

Product

Resources

About