Automatic gate-level synthesis of speed-independent circuits

Abstract

In this paper, we present a CAD tool for the synthesis of asynchronous control circuits using basic gates such as AND gates and OR gates. The synthesized circuits are speed-independent; that is, they work correctly regardless of individual gate delays. We present synthesis results for a variety of specifications taken from industry and previously published examples. We compare our speed-independent circuits with those non-speedindependent circuits synthesized using the algorithms described in [ I ] , in which delay elements are added to remove circuit hazardr. These synthesis results show that our circuits are on average approximately 25% faster with an area penalty of only IS%. This work demonstrates that direct synthesis of gate-level speed-independent circuits is not only feasible, but also produces robust and relatively efJrcient circuits compared to those synthesized with timing constraints.

A Methodology for Correct-by-Construction Latency Insensitive Design

“…By slightly relaxing the unbounded delay model and allowing "isochronic forks" 2 , practical quasi-delay-insensitive circuits can be built using simple logic gates [3]. A further relaxation leads to speed independent circuits, which operate correctly regardless of gate delays, while wire delays are assumed to be negligible [1,12,20]. Both quasidelay-insensitive and speed-independent circuits assume that the designer is able to control wire delays, and, therefore, do not appear as interesting alternatives when moving to DSM implementations.…”

“…Such shells can be automatically generated for all modules if the output of the module is latched and each module is stallable [4]. "Stallability" means that a module can stall for an arbitrary amount of clock cycles without losing its internal state and the overall state of the system and is much weaker than patience 1 . 1 Observe that most hardware systems can be easily made stallable: for instance, consider any sequential logic block together with a gated clock mechanism, or a Moore finite state machine with an extra input, that can force it to stay in the current state while emitting a "flag signal".…”

Decomposition Methods For Library Binding Of Speed-independent Asynchronous Designs

“…Varshavsky [17] showed that an implementation using n-input AND-OR-NOT gates or two-input NAND and NOR gates (with limited fanout) can be derived from any speed-independent signal transition graph (STG) without choice. These circuits are larger and more complex than those produced by Beerel's synthesis procedure [1], which uses unlimited-fanout basic gates to produce a hazard-free speed-independent design. No method addresses the general library binding problem, however.…”

“…This implementation may have been synthesized from a semi-modular speed-independent signal transition graph or state graph ( [3], [10], [1]), or may have been derived by some other means. Although the specification style is not important, knowledge of the environment is necessary to perform library binding for this design style.…”

“…Several researchers have tackled gate-level synthesis of speedindependent designs ( [17], [1]), although the gates may not be available in a particular library, due either to their complexity or their size. Varshavsky [17] showed that an implementation using n-input AND-OR-NOT gates or two-input NAND and NOR gates (with limited fanout) can be derived from any speed-independent signal transition graph (STG) without choice.…”