Decomposition Methods For Library Binding Of Speed-independent Asynchronous Designs

Abstract

We describe methods for decomposing gates within a speedindependent asynchronous design. The decomposition step is an essential part of the library binding process, and is used both to increase the granularity of the design for higher quality mapping and to ensure that the design can be implemented. We present algorithms for simple hazard-free gate decomposition, and show results which indicate that we can decompose most of the gates in our benchmark set by this simple method. We then extend these algorithms to work for those cases in which no simple decomposition exists.

Technology mapping for speed-independent circuits: Decomposition and resynthesis

“…Only one 5-input AND gate in pe-send-ifc and two 5-literal gates in tsend-bm were not decomposed when attempting to implement these circuits with 4-literal gates. We significantly improve over the results presented in [15], and only one circuit @e-rcv-$ I could not be realized with 2-literal gates from that benchmark suite.…”

“…The number of inserted signals shows also the number of iterations in technology mapping --the circuit is resynthesized every time a new signal is inserted. The next column summarizes the results presented by Siegel [15] with only 2-input gates. All realizations have been verified to be speed-independent.…”

“…The insertion of a new latch was crucial to allow the decomposition of a gate that could not be decomposed by the approach presented in [15].…”

“…For example, the approach described in [16] works only under thefundamental mode assumption, which is overly restrictive and does not fit well theoretically with the unbounded delay assumption. The same authors describe in [15] a method to perform technology mapping for speed-independent circuits that only decomposes existing gates (e.g., a 3-input AND into two 2-inputANDs), without any further search of the implementation space. They do not explore complex decompositions, that could use multi-cube divisors, or decompose several gates simultaneously.…”

Partial order based approach to synthesis of speed-independent circuits

“…Later techniques, e.g. [16,6], attempt to decompose the complex gates preserving the speed-independence 1 of the circuit.…”