Structural methods for the synthesis of speed-independent circuits

Pastor, Enric; Cortadella, Jordi; Kondratyev, A.; Roig, O.

doi:10.1109/43.736185

Cited by 26 publications

(19 citation statements)

References 36 publications

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“…An STG satisfying the output-semimodularity, consistency and CSC properties is called an implementable STG, from which a correct SI circuit can be derived [12]. Two transitions and are said to be concurrent if they can fire in the same marking without disabling each other and they are autoconcurrent [16] if they are of the same signal. Signal is said to be concurrent to a transition if there exists some transition of concurrent to .…”

Section: A Pns and Stgsmentioning

confidence: 99%

“…A transition is a context transition (and its underling signal a context signal) of a transition if signal is nonconcurrent to and any transition that is interleaved with ( ) is not of the same signal as or . Owing to the characteristic of a C element that the two input values are allowed to be identical at the same time, the markings covered by , under some constraints, may be extended to include the markings in QR [16] for circuit implementability or area saving. Since the outputs of the first-level AND gates in the standard C implementation are one-hot encoded, the SI property is still preserved if any valid Boolean decomposition is applied to the second-level OR gates [19].…”

Section: ) One-hot Conditionmentioning

confidence: 99%

“…To perform our decomposition and resynthesis work at the STG level, some cube properties are analyzed in this section. The formulation is borrowed from [16] with some adjustments to make it more suitable for our discussion.…”

Section: Cube Properties For Processing At Stg Levelmentioning

confidence: 99%

“…Moreover, due to the high-level property of an STG, it is also easier for designers to describe the circuit behavior. Thanks to these properties of an STG, it has been previously applied in solving the state conflict problem and synthesizing the SI circuits [2], [4], [10], [15], [16], [20]. To our knowledge, however, no work has been constructed at the STG level for the decomposition and resynthesis of SI circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Then, for those high-fanin gates, the combinational decomposition is performed to decompose them into some low-fanin ones. To avoid an explicit generation of all the markings in an STG, some properties peculiar to cubes are analyzed with the help of the concurrency [4] and interleave [16] relations between signals. Since the resynthesis cycles constitute a major part of the run time, they are reduced in our method by first finding a hazard-free decomposition of each high-fanin gate without adding any signals to the STG.…”

Section: Introductionmentioning

confidence: 99%

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STG-level decomposition and resynthesis of speed-independent circuits

Chen

Jou

2002

IEEE Trans. Circuits Syst. I

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This paper presents a time-efficient method for the decomposition and resynthesis of speed-independent (SI) circuits. Given the specification of an SI circuit, our method first generates its standard C implementation. Then, the combinational decomposition is performed to decompose each high-fanin gate that does not exist in the gate library into some available low-fanin gates. The time efficiency of our method is achieved in two ways. First, the signal transition graph (STG), whose complexity is polynomial in the worst case, is adopted as our input specification. Second, to reduce the resynthesis cycles, which constitute a major part of the run time, our method first investigates the hazard-free decomposition of each high-fanin gate without adding any signals. Then, for those gates that cannot be decomposed hazard free, two signal-adding methods constructed at the STG level are developed for resynthesis. This decomposition and resynthesis process is iterated until all high-fanin gates are successfully decomposed or no solution can be found. Several experiments have been done on the asynchronous benchmarks and it can be seen from the results that our method largely reduces the run time only at a little more area expense when compared with previous work.Index Terms-Hazard-free decomposition, resynthesis, signal transition graph (STG), speed-independent (SI) circuit.

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Section: A Pns and Stgsmentioning

confidence: 99%

Section: ) One-hot Conditionmentioning

confidence: 99%

Section: Cube Properties For Processing At Stg Levelmentioning

confidence: 99%