A Methodology for Correct-by-Construction Latency Insensitive Design

Carloni, Luca P.; McMillan, Kenneth L.; Saldanha, A.; Sangiovanni‐Vincentelli, Alberto

doi:10.1007/978-1-4615-0292-0_12

Cited by 30 publications

(59 citation statements)

References 25 publications

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“…To efficiently source and sink data, two stream engines are employed with a FIFO capacity of 256x32 bit each. The test platform was an ACE-V ACS [16]. The relevant platform HW used here includes a 100MHz microSPARC IIep CPU with 64 MB of DRAM and a Virtex 1000 -4 FPGA.…”

Section: Hardware Experimental Resultsmentioning

confidence: 99%

HW/SW Co-design by Automatic Embedding of Complex IP Cores

Lange

Koch

2004

Field Programmable Logic and Application

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Section: Hardware Experimental Resultsmentioning

confidence: 99%

HW/SW Co-design by Automatic Embedding of Complex IP Cores

Lange

Koch

2004

Field Programmable Logic and Application

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“…Hence, it is not surprising that the maximum number of hops at 45nm does not change much across the various router configurations because intermediate stateful repeaters such as relay stations [37] are needed to segment long interconnection links. The use of larger routers does not help to reduce the number of hops while it increases the chance of contention.…”

Section: Hop Countmentioning

confidence: 99%

A Methodology for Constraint-Driven Synthesis of On-Chip Communications

Pinto¹,

Carloni

Sangiovanni-Vincentelli

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a target library. Models for functionality, cost, and performance of each element are captured in the library together with their composition rules. We develop a mathematical framework to model communication at different levels of abstraction from the point-to-point input specification to the library elements and the final implementation.

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“…A slightly modified version of a relay station [6] is used to prevent data loss when the successor primitive is full. Figure 2 illustrates the switching primitives in our MoT network.…”

Section: Memorymentioning

confidence: 99%