Atomistic approach to variability of bias-temperature instability in circuit simulations

Kaczer, B.; Mahato, Swaraj Bandhu; Camargo, Vinícius V. A.; Toledano-Luque, M.; Roussel, Ph.; Grasser, T.; Catthoor, Francky; Dobrovolný, Petr; Zuber, Paul; Wirth, Gilson; Groeseneken, G.

doi:10.1109/irps.2011.5784604

Cited by 109 publications

(86 citation statements)

References 11 publications

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“…As discussed in [4][5], the threshold voltage degradation of small-geometry devices shows significant levels of uncertainty due to the random nature of the spatial distribution of defects in the dielectric, as well as the impact on Δ of each defect. Under the charge trapping model for BTI, each MOS device is characterized by the number of defects, the capture and emission time of each defect, and the impact on device when each defect is charged [4].…”

Section: A Bti Variability Under Charge Trapping Modelmentioning

confidence: 99%

“…Under the charge trapping model for BTI, each MOS device is characterized by the number of defects, the capture and emission time of each defect, and the impact on device when each defect is charged [4]. These defect parameters are characterized in device experiments for given semiconductor technology using the recently-proposed timedependent defect spectroscopy (TDDS) method [6].…”

Section: A Bti Variability Under Charge Trapping Modelmentioning

confidence: 99%

“…Based on the charge trapping model, the intrinsic variability of BTI effect was explored analytically in [3], which indicates the possibility of very large device-level variations for smallgeometry FETs, leading to orders-of-magnitude lifetime variations. These models were incorporated in a circuit simulator [4] and demonstrated on an inverter circuit, predicting large delay variations (with / of over 20%). However the proposed approaches in [4] were based on SPICElike circuit simulation that feeds a Monte Carlo method, and this approach is not scalable to large-scale digital circuits.…”

Section: Introductionmentioning

confidence: 99%

“…These models were incorporated in a circuit simulator [4] and demonstrated on an inverter circuit, predicting large delay variations (with / of over 20%). However the proposed approaches in [4] were based on SPICElike circuit simulation that feeds a Monte Carlo method, and this approach is not scalable to large-scale digital circuits. A significant unanswered question, which this paper attempts to address, is: how does this large device-level variation translate to variations at the circuit level?…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Understanding the impact of transistor-level BTI variability

Fang

Sapatnekar

2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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Abstract-Recent work has shown large variations due to biastemperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability at the circuit level is significantly smaller than at the device level, but increases with device downscaling.

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Section: A Bti Variability Under Charge Trapping Modelmentioning

confidence: 99%

Section: A Bti Variability Under Charge Trapping Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Understanding the impact of transistor-level BTI variability

Fang

Sapatnekar

2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…The BTI effect increases the threshold voltage (|V t |) of a MOS transistor, resulting in a time-dependent timing degradation in very large scale integrated (VLSI) circuits [8] [7]. It is mandatory to consider the BTI effect in modern timing signoff recipes -via 10-year timing libraries, flat V DD margin, etc.…”

Section: Introductionmentioning

confidence: 99%

Impact of Adaptive Voltage Scaling on Aging-Aware Signoff

Chan¹,

Chan²,

Kahng³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32nm technology. Aging decreases performance of digital circuits over the entire IC lifetime. To compensate for aging, designs now typically apply adaptive voltage scaling (AVS) to mitigate performance degradation by elevating supply voltage. Varying the supply voltage of a circuit using AVS also causes the BTI degradation to vary over lifetime. This presents a new challenge for margin reduction in conventional signoff methodology, which characterizes timing libraries based on transistor models with pre-calculated BTI degradations for a given IC lifetime. Many works have separately addressed predictive models of BTI and the analysis of AVS, but there is no published work that considers BTI-aware signoff that accounts for the use of AVS during IC lifetime. This motivates us to study how the presence of AVS should affect aging-aware signoff. In this paper, we first simulate and analyze circuit performance degradation due to BTI in the presence of AVS. Based on our observations, we propose a ruleof-thumb for chip designers to characterize an aging-derated standardcell timing library that accounts for the impact of AVS. According to our experimental results, this aging-aware signoff approach avoids both overestimation and underestimation of aging -either of which results in power or area penalty -in AVS enabled systems.

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The Capture/Emission Time Map Approach to the Bias Temperature Instability

Grasser

2013

Bias Temperature Instability for Devices and Circuits

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Atomistic approach to variability of bias-temperature instability in circuit simulations

Cited by 109 publications

References 11 publications

Understanding the impact of transistor-level BTI variability

Understanding the impact of transistor-level BTI variability

Impact of Adaptive Voltage Scaling on Aging-Aware Signoff

The Capture/Emission Time Map Approach to the Bias Temperature Instability

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